From patchwork Mon Oct 31 12:33:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 1697177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=daynix-com.20210112.gappssmtp.com header.i=@daynix-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=u2birZTK; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N1CM910jnz23l6 for ; Mon, 31 Oct 2022 23:36:35 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU0k-0005gD-Nx; Mon, 31 Oct 2022 08:35:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzl-0003WF-5L for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:29 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTzh-0004Ok-Ot for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:34:24 -0400 Received: by mail-pj1-x1031.google.com with SMTP id k5so2700559pjo.5 for ; Mon, 31 Oct 2022 05:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rOjHWNXn/Wht1Shk+YGDnbsD8G3ScWO/Koc/z3Bsls4=; b=u2birZTKvuAI0Mbv1QJ6/Bz86V7LFLywE5wgKFdVyqk1JoCo0/SNwNIqsDqKzlqKo3 QOx4TdpNAfH2cVpNOx4q82G7zTpcf9aKpZPOodHy4y9cKybPMFN21JWsem9OXMYy/D+O Z+xeks7RP/80UoDmz5sM5qCXoFq3USY17iCeIkUQaR6IBMn04FohspNSY/D89qwK8PaI LNcAaXJqLxbPQ73eZ9OCLudBxl6qFaNlqEw9egJ9tP7CGhVpmVbloeu2dM4jw5NaNSpr dUj1C33WOr4KVWiJMW5RPGrx/WluEigeGDqh0R24vGGrTRDKrtF8jiWUrIFy5HlfXtr+ D/ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rOjHWNXn/Wht1Shk+YGDnbsD8G3ScWO/Koc/z3Bsls4=; b=QnTbdaXMgi/fq4fu8DQFqLKLD3bqTFOdVLp5cFl3o6McK170dMzQj7fgLN4+TKSdHC X7CfzXr1gwP/wGu0HPClNAdzskUQJzj5ClZUBMpYD8CNTEzcW6CYLAMoWv4GnH5L5EOH B1Ts9O9/gOZjD/qfvf4o//9okeH2HGW28o/X3trfmMeUjoLq+sQVmDl1qeKB+5850RC+ zAV5JKLPFxnr0g/Gu8irgVG0IBAsgL2703FOYyygLjXdVZYObBQ+IqF2C79QEv8E/L2w 3gGBBFcXaR7YTCS9AEv7m4ijcrZ6RFZVEHmEnIN24Y8yx9icF0nQYjvxhU6nUaV6qVMk k8Jg== X-Gm-Message-State: ACrzQf3bvUVIJ4cYHBle1Ja7Q6lylDN6WiSSUGER7tO4/d37H5nC92jx MZaubZFmKdvwb2gDNPqdTjVMBfRtwtN06/cP X-Google-Smtp-Source: AMsMyM6laLIML14feAWb6f51TQkKT23fSKTAFvnm4U8aTlfs02uM3r2mszeJSuYos1GDQe8Zn6/qVQ== X-Received: by 2002:a17:902:f68f:b0:186:9b98:8d8a with SMTP id l15-20020a170902f68f00b001869b988d8amr13975971plg.59.1667219649515; Mon, 31 Oct 2022 05:34:09 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:34:08 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 08/17] msi: Omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:10 +0900 Message-Id: <20221031123319.21532-9-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::1031; envelope-from=akihiko.odaki@daynix.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org Omitting errp for pci_add_capability() causes it to abort if capabilities overlap. A caller of msi_init(), which calls pci_add_capability() in turn, is expected to ensure that will not happen. Signed-off-by: Akihiko Odaki --- hw/pci/msi.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/pci/msi.c b/hw/pci/msi.c index 058d1d1ef1..5283a08b5a 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -194,7 +194,6 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int vectors_order; uint16_t flags; uint8_t cap_size; - int config_offset; if (!msi_nonbroken) { error_setg(errp, "MSI is not supported by interrupt controller"); @@ -221,13 +220,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } cap_size = msi_cap_sizeof(flags); - config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, - cap_size, errp); - if (config_offset < 0) { - return config_offset; - } - - dev->msi_cap = config_offset; + dev->msi_cap = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size); dev->cap_present |= QEMU_PCI_CAP_MSI; pci_set_word(dev->config + msi_flags_off(dev), flags);