From patchwork Mon Oct 31 12:33:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akihiko Odaki X-Patchwork-Id: 1697174 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=daynix-com.20210112.gappssmtp.com header.i=@daynix-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=TqvCcYQd; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4N1CKL5lgYz23lV for ; Mon, 31 Oct 2022 23:35:00 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1opU07-0003t5-Pl; Mon, 31 Oct 2022 08:34:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1opTzA-00033s-6B for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:50 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1opTz2-0004JJ-R3 for qemu-devel@nongnu.org; Mon, 31 Oct 2022 08:33:45 -0400 Received: by mail-pg1-x533.google.com with SMTP id q1so10548228pgl.11 for ; Mon, 31 Oct 2022 05:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=daynix-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RVbq2yaYdJoiH8651nfM6y1MMdPJwfTDDNgpcpWTQtU=; b=TqvCcYQdwxQnOH+f5Jnf35dTOjiAWR9ZHIWaZ2K8yO9K5FLM870HN1y7NZuo20+6TU VJpLZoIbES71DtaOsEVKUYLCml8kYODj9zNFN3OjPV8uXercAcFppZcw6z33xcIJxTyU 7De0A/fA09Oz+kXmVyzju2tZMIIUtvu62CBBi51i1uHgJmEa0bugvEe409dt47yqCPwx OrKJKwp6fNPSEMSDK30AVEVxDBr2CwHRJxAswAfrjioUCVjdMqV3p4k4P1s9p+kcPZ/Z us1r82ckfgAmV2uJxX/IyJni1cp4SCqjyzZ3/VHEEARXpEXsibLo6m56TGkhbnKXISIz lyWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RVbq2yaYdJoiH8651nfM6y1MMdPJwfTDDNgpcpWTQtU=; b=ARXeWILgRm2VzywWCGZLFiZpOFMLWtvLz/wJd65RdCawA4I/ldvOi18sL4wG2buVm3 Y5zkygEAwx/s3NYzeYiLwwVYIzzR1rAp9SGzWffBK1QPUqmZDoBuznjp5D8tsoJnkwgM /YsP2i+QIik2l9hoGqw4TP8ODCUExZs5LZdswNA1iOWDOr4QPvCHFlhMm8PYBCl52Z/Q XUFlaba44hrSLHj0K+MS2wau4Gve5csGOC33O3m1x9MvK6gs29IRyNWPyomqIfilJ1o4 SYGmDwESr2V+IzWibuXLL+y82qnPCw7HHaU3Lmcx9hQkaUsymaqMuthGqMNoaawcq6BT yXnA== X-Gm-Message-State: ACrzQf1FM1cW4Yy1rqrM4jcZLfQaea75FNGdoiHKd71+gqjDJFwKtJcc cgfaR+secGKT6UCkGxjGCRic3GBXH0hLfOkC X-Google-Smtp-Source: AMsMyM6rl6PxU6g1thJbovWYQzihw6qwr5+kDlaP/CSrje/rSUl9P6QFkvywMlhHkL9lnzG5beYOHA== X-Received: by 2002:a62:582:0:b0:56c:8c13:247e with SMTP id 124-20020a620582000000b0056c8c13247emr14028286pff.43.1667219618812; Mon, 31 Oct 2022 05:33:38 -0700 (PDT) Received: from fedora.flets-east.jp ([2400:4050:c360:8200:8ae8:3c4:c0da:7419]) by smtp.gmail.com with ESMTPSA id m10-20020a6545ca000000b0042b5095b7b4sm4093810pgr.5.2022.10.31.05.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Oct 2022 05:33:38 -0700 (PDT) From: Akihiko Odaki To: Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, "Michael S . Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann , Paolo Bonzini , Richard Henderson , Eduardo Habkost , John Snow , Dmitry Fleytman , Jason Wang , Stefan Weil , Keith Busch , Klaus Jensen , Peter Maydell , Andrey Smirnov , Paul Burton , Aleksandar Rikalo , Yan Vugenfirer , Yuri Benditovich , Akihiko Odaki Subject: [PATCH v6 02/17] pci: Allow to omit errp for pci_add_capability Date: Mon, 31 Oct 2022 21:33:04 +0900 Message-Id: <20221031123319.21532-3-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221031123319.21532-1-akihiko.odaki@daynix.com> References: <20221031123319.21532-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::533; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org+incoming=patchwork.ozlabs.org@nongnu.org pci_add_capability appears most PCI devices. Its error handling required lots of code, and led to inconsistent behaviors such as: - passing error_abort - passing error_fatal - asserting the returned value - propagating the error to the caller - skipping the rest of the function - just ignoring The code generating errors in pci_add_capability had a comment which says: > Verify that capabilities don't overlap. Note: device assignment > depends on this check to verify that the device is not broken. > Should never trigger for emulated devices, but it's helpful for > debugging these. Indeed vfio has some code that passes capability offsets and sizes from a physical device, but it explicitly pays attention so that the capabilities never overlap. Therefore, we can always assert that capabilities never overlap when pci_add_capability is called, resolving these inconsistencies. Such an implementation of pci_add_capability will not have errp parameter. However, there are so many callers of pci_add_capability that it does not make sense to amend all of them at once to match with the new signature. Instead, this change will allow callers of pci_add_capability to omit errp as the first step. Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 8 ++++---- include/hw/pci/pci.h | 13 ++++++++++--- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2f450f6a72..8ee2171011 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2513,14 +2513,14 @@ static void pci_del_option_rom(PCIDevice *pdev) } /* - * On success, pci_add_capability() returns a positive value + * On success, pci_add_capability_legacy() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp) { uint8_t *config; int i, overlapping_cap; diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index b54b6ef88f..51fd106f16 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -2,6 +2,7 @@ #define QEMU_PCI_H #include "exec/memory.h" +#include "qapi/error.h" #include "sysemu/dma.h" /* PCI includes legacy ISA access. */ @@ -390,9 +391,15 @@ void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, void pci_unregister_vga(PCIDevice *pci_dev); pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num); -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); +int pci_add_capability_legacy(PCIDevice *pdev, uint8_t cap_id, + uint8_t offset, uint8_t size, + Error **errp); + +#define PCI_ADD_CAPABILITY_VA(pdev, cap_id, offset, size, errp, ...) \ + pci_add_capability_legacy(pdev, cap_id, offset, size, errp) + +#define pci_add_capability(...) \ + PCI_ADD_CAPABILITY_VA(__VA_ARGS__, &error_abort) void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);