| Message ID | 20221020090455.2371099-2-yangxiaojuan@loongson.cn |
|---|---|
| State | New |
| Headers | show |
| Series | Fix LoongArch extioi coreisr accessing | expand |
On 20/10/22 11:04, Xiaojuan Yang wrote: > Converting the MemoryRegionOps read/write handlers to > with_attrs in LoongArch extioi emulation. > > Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> > --- > hw/intc/loongarch_extioi.c | 32 +++++++++++++++++--------------- > hw/intc/trace-events | 3 +-- > target/loongarch/iocsr_helper.c | 18 ++++++++++-------- > 3 files changed, 28 insertions(+), 25 deletions(-) > > diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c > index 22803969bc..16f2261844 100644 > --- a/hw/intc/loongarch_extioi.c > +++ b/hw/intc/loongarch_extioi.c > @@ -17,7 +17,6 @@ > #include "migration/vmstate.h" > #include "trace.h" > > - > static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) > { > int ipnum, cpu, found, irq_index, irq_mask; > @@ -68,44 +67,45 @@ static void extioi_setirq(void *opaque, int irq, int level) > extioi_update_irq(s, irq, level); > } > > -static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size) > +static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, > + unsigned size, MemTxAttrs attrs) > { > LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); > unsigned long offset = addr & 0xffff; > - uint32_t index, cpu, ret = 0; > + uint32_t index, cpu; > > switch (offset) { > case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: > index = (offset - EXTIOI_NODETYPE_START) >> 2; > - ret = s->nodetype[index]; > + *data = s->nodetype[index]; > break; > case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: > index = (offset - EXTIOI_IPMAP_START) >> 2; > - ret = s->ipmap[index]; > + *data = s->ipmap[index]; > break; > case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: > index = (offset - EXTIOI_ENABLE_START) >> 2; > - ret = s->enable[index]; > + *data = s->enable[index]; > break; > case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: > index = (offset - EXTIOI_BOUNCE_START) >> 2; > - ret = s->bounce[index]; > + *data = s->bounce[index]; > break; > case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: > index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2; > cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3; > - ret = s->coreisr[cpu][index]; > + *data = s->coreisr[cpu][index]; > break; > case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: > index = (offset - EXTIOI_COREMAP_START) >> 2; > - ret = s->coremap[index]; > + *data = s->coremap[index]; > break; > default: > break; > } > > - trace_loongarch_extioi_readw(addr, ret); > - return ret; > + trace_loongarch_extioi_readw(addr, *data); > + return MEMTX_OK; > } > > static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ > @@ -127,8 +127,9 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ > } > } > > -static void extioi_writew(void *opaque, hwaddr addr, > - uint64_t val, unsigned size) > +static MemTxResult extioi_writew(void *opaque, hwaddr addr, > + uint64_t val, unsigned size, > + MemTxAttrs attrs) > { > LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); > int i, cpu, index, old_data, irq; > @@ -231,11 +232,12 @@ static void extioi_writew(void *opaque, hwaddr addr, > default: > break; > } > + return MEMTX_OK; > } > > static const MemoryRegionOps extioi_ops = { > - .read = extioi_readw, > - .write = extioi_writew, > + .read_with_attrs = extioi_readw, > + .write_with_attrs = extioi_writew, > .impl.min_access_size = 4, > .impl.max_access_size = 4, > .valid.min_access_size = 4, > diff --git a/hw/intc/trace-events b/hw/intc/trace-events > index 0a90c1cdec..6fbc2045e6 100644 > --- a/hw/intc/trace-events > +++ b/hw/intc/trace-events > @@ -306,6 +306,5 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d" > > # loongarch_extioi.c > loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d" > -loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x" > +loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64 > loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64 > - Thanks for splitting. Up to here is the first patch, for it: Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Now what follows belongs to the next patch: > diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c > index 0e9c537dc7..dd34bb54e6 100644 > --- a/target/loongarch/iocsr_helper.c > +++ b/target/loongarch/iocsr_helper.c > @@ -14,54 +14,56 @@ > #include "exec/cpu_ldst.h" > #include "tcg/tcg-ldst.h" > > +#define GET_MEMTXATTRS(cs) ((MemTxAttrs) {.requester_id = cs->cpu_index}) Note, you could move the env_cpu() call to the macro to simplify: #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index}) > + > uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) > { > return address_space_ldub(&env->address_space_iocsr, r_addr, > - MEMTXATTRS_UNSPECIFIED, NULL); > + GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) > { > return address_space_lduw(&env->address_space_iocsr, r_addr, > - MEMTXATTRS_UNSPECIFIED, NULL); > + GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) > { > return address_space_ldl(&env->address_space_iocsr, r_addr, > - MEMTXATTRS_UNSPECIFIED, NULL); > + GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) > { > return address_space_ldq(&env->address_space_iocsr, r_addr, > - MEMTXATTRS_UNSPECIFIED, NULL); > + GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr, > target_ulong val) > { > address_space_stb(&env->address_space_iocsr, w_addr, > - val, MEMTXATTRS_UNSPECIFIED, NULL); > + val, GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr, > target_ulong val) > { > address_space_stw(&env->address_space_iocsr, w_addr, > - val, MEMTXATTRS_UNSPECIFIED, NULL); > + val, GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr, > target_ulong val) > { > address_space_stl(&env->address_space_iocsr, w_addr, > - val, MEMTXATTRS_UNSPECIFIED, NULL); > + val, GET_MEMTXATTRS(env_cpu(env)), NULL); > } > > void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr, > target_ulong val) > { > address_space_stq(&env->address_space_iocsr, w_addr, > - val, MEMTXATTRS_UNSPECIFIED, NULL); > + val, GET_MEMTXATTRS(env_cpu(env)), NULL); > }
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index 22803969bc..16f2261844 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -17,7 +17,6 @@ #include "migration/vmstate.h" #include "trace.h" - static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level) { int ipnum, cpu, found, irq_index, irq_mask; @@ -68,44 +67,45 @@ static void extioi_setirq(void *opaque, int irq, int level) extioi_update_irq(s, irq, level); } -static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size) +static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); unsigned long offset = addr & 0xffff; - uint32_t index, cpu, ret = 0; + uint32_t index, cpu; switch (offset) { case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1: index = (offset - EXTIOI_NODETYPE_START) >> 2; - ret = s->nodetype[index]; + *data = s->nodetype[index]; break; case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: index = (offset - EXTIOI_IPMAP_START) >> 2; - ret = s->ipmap[index]; + *data = s->ipmap[index]; break; case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1: index = (offset - EXTIOI_ENABLE_START) >> 2; - ret = s->enable[index]; + *data = s->enable[index]; break; case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1: index = (offset - EXTIOI_BOUNCE_START) >> 2; - ret = s->bounce[index]; + *data = s->bounce[index]; break; case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1: index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2; cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3; - ret = s->coreisr[cpu][index]; + *data = s->coreisr[cpu][index]; break; case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1: index = (offset - EXTIOI_COREMAP_START) >> 2; - ret = s->coremap[index]; + *data = s->coremap[index]; break; default: break; } - trace_loongarch_extioi_readw(addr, ret); - return ret; + trace_loongarch_extioi_readw(addr, *data); + return MEMTX_OK; } static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ @@ -127,8 +127,9 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\ } } -static void extioi_writew(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static MemTxResult extioi_writew(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + MemTxAttrs attrs) { LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque); int i, cpu, index, old_data, irq; @@ -231,11 +232,12 @@ static void extioi_writew(void *opaque, hwaddr addr, default: break; } + return MEMTX_OK; } static const MemoryRegionOps extioi_ops = { - .read = extioi_readw, - .write = extioi_writew, + .read_with_attrs = extioi_readw, + .write_with_attrs = extioi_writew, .impl.min_access_size = 4, .impl.max_access_size = 4, .valid.min_access_size = 4, diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 0a90c1cdec..6fbc2045e6 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -306,6 +306,5 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d" # loongarch_extioi.c loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d" -loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x" +loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64 - diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c index 0e9c537dc7..dd34bb54e6 100644 --- a/target/loongarch/iocsr_helper.c +++ b/target/loongarch/iocsr_helper.c @@ -14,54 +14,56 @@ #include "exec/cpu_ldst.h" #include "tcg/tcg-ldst.h" +#define GET_MEMTXATTRS(cs) ((MemTxAttrs) {.requester_id = cs->cpu_index}) + uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldub(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + GET_MEMTXATTRS(env_cpu(env)), NULL); } uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr) { return address_space_lduw(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + GET_MEMTXATTRS(env_cpu(env)), NULL); } uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldl(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + GET_MEMTXATTRS(env_cpu(env)), NULL); } uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr) { return address_space_ldq(&env->address_space_iocsr, r_addr, - MEMTXATTRS_UNSPECIFIED, NULL); + GET_MEMTXATTRS(env_cpu(env)), NULL); } void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stb(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, GET_MEMTXATTRS(env_cpu(env)), NULL); } void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stw(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, GET_MEMTXATTRS(env_cpu(env)), NULL); } void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stl(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, GET_MEMTXATTRS(env_cpu(env)), NULL); } void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr, target_ulong val) { address_space_stq(&env->address_space_iocsr, w_addr, - val, MEMTXATTRS_UNSPECIFIED, NULL); + val, GET_MEMTXATTRS(env_cpu(env)), NULL); }
Converting the MemoryRegionOps read/write handlers to with_attrs in LoongArch extioi emulation. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> --- hw/intc/loongarch_extioi.c | 32 +++++++++++++++++--------------- hw/intc/trace-events | 3 +-- target/loongarch/iocsr_helper.c | 18 ++++++++++-------- 3 files changed, 28 insertions(+), 25 deletions(-)