From patchwork Wed Oct 5 14:37:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?V=C3=ADctor_Colombo?= X-Patchwork-Id: 1686393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4MjJR24SXYz23jM for ; Thu, 6 Oct 2022 02:29:48 +1100 (AEDT) Received: from localhost ([::1]:47506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1og6LA-0003Yc-EY for incoming@patchwork.ozlabs.org; Wed, 05 Oct 2022 11:29:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1og5Xl-0005xL-B3; Wed, 05 Oct 2022 10:38:42 -0400 Received: from [200.168.210.66] (port=55228 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1og5Xj-0004bx-MA; Wed, 05 Oct 2022 10:38:41 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Wed, 5 Oct 2022 11:37:24 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 9116A8003B3; Wed, 5 Oct 2022 11:37:23 -0300 (-03) From: =?utf-8?q?V=C3=ADctor_Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, aurelien@aurel32.net, peter.maydell@linaro.org, alex.bennee@linaro.org, balaton@eik.bme.hu, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, leandro.lupori@eldorado.org.br, lucas.coutinho@eldorado.org.br Subject: [RFC PATCH 2/4] target/ppc: Implement instruction caching for fsqrt Date: Wed, 5 Oct 2022 11:37:17 -0300 Message-Id: <20221005143719.65241-3-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221005143719.65241-1-victor.colombo@eldorado.org.br> References: <20221005143719.65241-1-victor.colombo@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 05 Oct 2022 14:37:24.0205 (UTC) FILETIME=[FBCD31D0:01D8D8C7] X-Host-Lookup-Failed: Reverse DNS lookup failed for 200.168.210.66 (failed) Received-SPF: pass client-ip=200.168.210.66; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This patch adds the code necessary to cache fsqrt for usage with hardfpu in Power. It is also the first instruction to use the new cache instruction system. fsqrt is an instruction that receives two arguments, one f64 and one status, and returns f64. This info will be cached inside a new union in env, which will grow when other instructions with other signatures are added. Hardfpu in QEMU only works when the inexact is already set. So, CACHE_FN_3 will check if FP_XX is set, and set float_flag_inexact to enable the hardfpu behavior. When the instruction is later reexecuted, it will be with float_flag_inexact cleared, forcing softfloat and correctly updating the relevant flags, as is today. Signed-off-by: Víctor Colombo --- target/ppc/cpu.h | 11 +++++++++++ target/ppc/fpu_helper.c | 39 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1132d60162..b423e33a0c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1082,6 +1082,14 @@ struct ppc_radix_page_info { enum { CACHED_FN_TYPE_NONE, + CACHED_FN_TYPE_F64_F64_FSTATUS, + +}; + +struct cached_fn_f64_f64_fstatus { + float64 (*fn)(float64, float_status*); + float64 arg1; + float_status arg2; }; struct CPUArchState { @@ -1162,6 +1170,9 @@ struct CPUArchState { target_ulong fpscr; /* Floating point status and control register */ int cached_fn_type; + union { + struct cached_fn_f64_f64_fstatus f64_f64_fstatus; + } cached_fn; /* Internal devices resources */ ppc_tb_t *tb_env; /* Time base and decrementer */ diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 6aaee37619..b68f12a1a9 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -30,6 +30,21 @@ env->cached_fn_type = CACHED_FN_TYPE_NONE; \ } while (0) +#define CACHE_FN_3(env, FN, ARG1, ARG2, FIELD, TYPE) \ + do { \ + if (env->fpscr & FP_XX) { \ + env->cached_fn_type = TYPE; \ + env->cached_fn.FIELD.fn = FN; \ + env->cached_fn.FIELD.arg1 = ARG1; \ + env->cached_fn.FIELD.arg2 = ARG2; \ + env->fp_status.float_exception_flags |= float_flag_inexact; \ + } else { \ + assert(!(env->fp_status.float_exception_flags & \ + float_flag_inexact)); \ + env->cached_fn_type = CACHED_FN_TYPE_NONE; \ + } \ + } while (0) + static inline float128 float128_snan_to_qnan(float128 x) { float128 r; @@ -530,6 +545,27 @@ void helper_execute_fp_cached(CPUPPCState *env) * so no need to execute it again */ break; + case CACHED_FN_TYPE_F64_F64_FSTATUS: + /* + * execute the cached insn. At this point, float_exception_flags + * should have FI not set, otherwise the result will not be correct + */ + assert((env->cached_fn.f64_f64_fstatus.arg2.float_exception_flags & + float_flag_inexact) == 0); + env->cached_fn.f64_f64_fstatus.fn( + env->cached_fn.f64_f64_fstatus.arg1, + &env->cached_fn.f64_f64_fstatus.arg2); + + env->fpscr &= ~FP_FI; + /* + * if the cached instruction resulted in FI being set + * then we update fpscr with this value + */ + if (env->cached_fn.f64_f64_fstatus.arg2.float_exception_flags & + float_flag_inexact) { + env->fpscr |= FP_FI | FP_XX; + } + break; default: g_assert_not_reached(); } @@ -872,7 +908,8 @@ static void float_invalid_op_sqrt(CPUPPCState *env, int flags, #define FPU_FSQRT(name, op) \ float64 helper_##name(CPUPPCState *env, float64 arg) \ { \ - CACHE_FN_NONE(env); \ + CACHE_FN_3(env, op, arg, env->fp_status, f64_f64_fstatus, \ + CACHED_FN_TYPE_F64_F64_FSTATUS); \ float64 ret = op(arg, &env->fp_status); \ int flags = get_float_exception_flags(&env->fp_status); \ \