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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:55 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?utf-8?q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 6 Sep 2022 14:22:38 +0200 Message-Id: <20220906122243.1243354-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=christoph.muellner@vrull.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 67 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 3 + target/riscv/xtheadmac.decode | 30 ++++++++++ 6 files changed, 103 insertions(+) create mode 100644 target/riscv/xtheadmac.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b7d6dbd28e..e2d74fa701 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,6 +925,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0b58b38335..d0dc4ab031 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,6 +445,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index da3a538400..fc8307b113 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -217,3 +217,70 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) { return gen_th_condmove(ctx, a, TCG_COND_NE); } + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp = tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 = tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd = rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd = rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 496ae37f26..55c019e55b 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,6 +7,7 @@ gen = [ decodetree.process('xtheadbs.decode', extra_args: '--static-decode=decode_xtheadbs'), decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=decode_xtheadcmo'), decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode=decode_xtheadcondmov'), + decodetree.process('xtheadmac.decode', extra_args: '--static-decode=decode_xtheadmac'), decodetree.process('xtheadsync.decode', extra_args: '--static-decode=decode_xtheadsync'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 986243df99..56cc89ce4a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -137,6 +137,7 @@ MATERIALISE_EXT_PREDICATE(xtheadbb) MATERIALISE_EXT_PREDICATE(xtheadbs) MATERIALISE_EXT_PREDICATE(xtheadcmo) MATERIALISE_EXT_PREDICATE(xtheadcondmov); +MATERIALISE_EXT_PREDICATE(xtheadmac); MATERIALISE_EXT_PREDICATE(xtheadsync) MATERIALISE_EXT_PREDICATE(XVentanaCondOps) @@ -729,6 +730,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) #include "decode-xtheadbs.c.inc" #include "decode-xtheadcmo.c.inc" #include "decode-xtheadcondmov.c.inc" +#include "decode-xtheadmac.c.inc" #include "decode-xtheadsync.c.inc" #include "decode-XVentanaCondOps.c.inc" @@ -1055,6 +1057,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { has_xtheadbs_p, decode_xtheadbs }, { has_xtheadcmo_p, decode_xtheadcmo }, { has_xtheadcondmov_p, decode_xtheadcondmov }, + { has_xtheadmac_p, decode_xtheadmac }, { has_xtheadsync_p, decode_xtheadsync }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xtheadmac.decode b/target/riscv/xtheadmac.decode new file mode 100644 index 0000000000..dda1f82334 --- /dev/null +++ b/target/riscv/xtheadmac.decode @@ -0,0 +1,30 @@ +# +# RISC-V instruction decode for the XTheadMac extension +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The XTheadMac extension provides multiply-accumulate instructions. +# +# It is documented in +# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats: +@r ..... .. ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# T-Head conditional move instructions +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r