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[77.183.70.107]) by smtp.gmail.com with ESMTPSA id o4-20020a170906768400b0073d7b876621sm2455758ejm.205.2022.08.22.15.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 15:44:46 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Jiaxun Yang , BALATON Zoltan , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Huacai Chen , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 2/9] hw/isa/vt82c686: Resolve unneeded attribute Date: Tue, 23 Aug 2022 00:43:48 +0200 Message-Id: <20220822224355.11753-3-shentey@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220822224355.11753-1-shentey@gmail.com> References: <20220822224355.11753-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that also the super io device is realized in the common realize method, the isa_bus attribute can be turned into a temporary. Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 0217c98fe4..9d12e1cae4 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -543,7 +543,6 @@ struct ViaISAState { PCIDevice dev; qemu_irq cpu_intr; qemu_irq *isa_irqs; - ISABus *isa_bus; ViaSuperIOState via_sio; }; @@ -585,17 +584,18 @@ static void via_isa_realize(PCIDevice *d, Error **errp) ViaISAState *s = VIA_ISA(d); DeviceState *dev = DEVICE(d); qemu_irq *isa_irq; + ISABus *isa_bus; int i; qdev_init_gpio_out(dev, &s->cpu_intr, 1); isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); - s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), + isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), &error_fatal); - s->isa_irqs = i8259_init(s->isa_bus, *isa_irq); - isa_bus_irqs(s->isa_bus, s->isa_irqs); - i8254_pit_init(s->isa_bus, 0x40, 0, NULL); - i8257_dma_init(s->isa_bus, 0); - mc146818_rtc_init(s->isa_bus, 2000, NULL); + s->isa_irqs = i8259_init(isa_bus, *isa_irq); + isa_bus_irqs(isa_bus, s->isa_irqs); + i8254_pit_init(isa_bus, 0x40, 0, NULL); + i8257_dma_init(isa_bus, 0); + mc146818_rtc_init(isa_bus, 2000, NULL); for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { @@ -604,7 +604,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) } /* Super I/O */ - if (!qdev_realize(DEVICE(&s->via_sio), BUS(s->isa_bus), errp)) { + if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) { return; } }