From patchwork Sat Aug 13 11:26:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Kochkov X-Patchwork-Id: 1666049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; secure) header.d=proton.me header.i=@proton.me header.a=rsa-sha256 header.s=protonmail header.b=UMA8qiaZ; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M4dcD72XMz9sGP for ; Sat, 13 Aug 2022 21:29:31 +1000 (AEST) Received: from localhost ([::1]:35360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMpKX-0004DR-LI for incoming@patchwork.ozlabs.org; Sat, 13 Aug 2022 07:29:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45850) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMpIW-0004DC-9a; Sat, 13 Aug 2022 07:27:20 -0400 Received: from mail-0201.mail-europe.com ([51.77.79.158]:48774) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMpIN-0002Kk-Nd; Sat, 13 Aug 2022 07:27:16 -0400 Date: Sat, 13 Aug 2022 11:26:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1660390021; x=1660649221; bh=Qdl3AKs8mRhBU+Ik9gzjoy7AEpjWD6DCO/69ZqSKWxI=; h=Date:To:From:Cc:Reply-To:Subject:Message-ID:Feedback-ID:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID; b=UMA8qiaZ3teD4qEXRXG5o5JLx3B0J3hfWsaE/kbSYYB8ya+BVpso+hcEHhkyC5sf1 eZlY/I0s+vV1LLL0+itRItZy832Iwe7RbgUSQG72K7f4S8Ey0WE8iydgC6knd9nM8t ggdIxu+R+zkHAN/xEW7HiCkK5rc6L2Uof7is7ONSqIW4I4QveC1L6HAre54CerXa4p hSCMvdZMIQdntDn/QrXxSCy3aJF77jXYlGGFVWkf/C5jMz7/FjHLVu6jydW/38wUuY tbxXznrwYrFHR8dDpPXgK+BGVEktBemDKPLBEj6k6u530vvKeBpPOsTL/1p+IKgrg4 PCNBHRicZJivQ== To: qemu-devel@nongnu.org From: Anton Kochkov Cc: Anton Kochkov , Peter Maydell , qemu-arm@nongnu.org Subject: [PATCH] hw/arm/nvic: implement "num-prio-bits" property Message-ID: <20220813112559.1974427-1-anton.kochkov@proton.me> Feedback-ID: 53490844:user:proton MIME-Version: 1.0 Received-SPF: pass client-ip=51.77.79.158; envelope-from=anton.kochkov@proton.me; helo=mail-0201.mail-europe.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Anton Kochkov Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Cortex-M NVIC can be configured with different amount of the maximum available priority bits. FreeRTOS has asserts that checks if the all unavailable priority bits are unset after writing into this register in real hardware. To allow setting this number depending on the machine or configuration expose priority bits as QDev property which is by default is set to 8 as it was hardcoded in the past. Thus, existing code doesn't require any additional changes, and it doesn't change the default behavior of NVIC. Signed-off-by: Anton Kochkov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 --- hw/intc/armv7m_nvic.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.37.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1f7763964c..b8959d645d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2580,6 +2580,8 @@ static const VMStateDescription vmstate_nvic = { static Property props_nvic[] = { /* Number of external IRQ lines (so excluding the 16 internal exceptions) */ DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), + /* Number of the maximum priority bits that can be used */ + DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 8), DEFINE_PROP_END_OF_LIST() }; @@ -2690,7 +2692,9 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) /* include space for internal exception vectors */ s->num_irq += NVIC_FIRST_IRQ; - s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7)) { + s->num_prio_bits = 2; + } /* * This device provides a single memory region which covers the