From patchwork Mon Aug 8 08:58:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 1664456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=KlDN8jPz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4M1VYG2sRSz9sB4 for ; Mon, 8 Aug 2022 19:01:06 +1000 (AEST) Received: from localhost ([::1]:49730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oKydE-0005MI-7L for incoming@patchwork.ozlabs.org; Mon, 08 Aug 2022 05:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKyay-0005JB-FX for qemu-devel@nongnu.org; Mon, 08 Aug 2022 04:58:45 -0400 Received: from mga09.intel.com ([134.134.136.24]:15916) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKyav-0001oV-MJ for qemu-devel@nongnu.org; Mon, 08 Aug 2022 04:58:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659949121; x=1691485121; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JoLhHDUQ0buGQR/L9NPQ9wh0/PiW8CiBoeswGZy+EaE=; b=KlDN8jPzlyNfcgZMGCBllVXsnzB7MzjHOhbyQp5LWQlpkisHAt2yBXpm oGOhe8FyQctFuDW2MTXaCjhDa2MYECOEovBXAsIuSD20ni0c9dr0ujVGa mLcANiHgh1WfichjRLHTBqxoAbwE+a3oewbKLR/wN3wrIqZ+zOCFgx5uB vJeipjo/s3bVUSmapuXoDFEeOr+yVCijwiTuyCXbM/eli9FasR4Y0dKhn kgiylWqcej431GZB+PKHHt0DXniF8Q75UqVHgFwhmpEzIqV1bVtW6s2Em cFgcFBC1M+DCJdbA95BpbrphUEjyKhVtauIXwuJUvrRsjd9hcyBE5cjng g==; X-IronPort-AV: E=McAfee;i="6400,9594,10432"; a="291319233" X-IronPort-AV: E=Sophos;i="5.93,221,1654585200"; d="scan'208";a="291319233" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 01:58:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,221,1654585200"; d="scan'208";a="931970551" Received: from lxy-dell.sh.intel.com ([10.239.48.38]) by fmsmga005.fm.intel.com with ESMTP; 08 Aug 2022 01:58:37 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v2 2/8] target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK Date: Mon, 8 Aug 2022 16:58:28 +0800 Message-Id: <20220808085834.3227541-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220808085834.3227541-1-xiaoyao.li@intel.com> References: <20220808085834.3227541-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.24; envelope-from=xiaoyao.li@intel.com; helo=mga09.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.998, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Per Intel SDM, bits 2:0 of CPUID(0x14,0x1).EAX indicate the number of address ranges for INTEL-PT. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f9646e16b872..fa02910ce811 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -570,7 +570,7 @@ static CPUCacheInfo legacy_l3_cache = { /* generated packets which contain IP payloads have LIP values */ #define INTEL_PT_IP_LIP (1 << 31) #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 +#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x7 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */