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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id k27-20020aa7999b000000b0052ab5740130sm71854pfh.37.2022.07.08.01.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 01:57:43 -0700 (PDT) From: Kito Cheng To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, liweiwei@iscas.ac.cn, richard.henderson@linaro.org Cc: Kito Cheng Subject: [PATCH 2/2] target/riscv: Implement dump content of vector register Date: Fri, 8 Jul 2022 16:57:36 +0800 Message-Id: <20220708085736.94546-2-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20220708085736.94546-1-kito.cheng@sifive.com> References: <20220708085736.94546-1-kito.cheng@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=kito.cheng@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Implement -d cpu,vu to dump content of vector register. Signed-off-by: Kito Cheng --- target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c1b96da7da..97b289d277 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = { "f30/ft10", "f31/ft11" }; +const char * const riscv_vr_regnames[] = { + "v0", "v1", "v2", "v3", "v4", "v5", + "v6", "v7", "v8", "v9", "v10", "v11", + "v12", "v13", "v14", "v15", "v16", "v17", + "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", + "v30", "v31" +}; + static const char * const riscv_excp_names[] = { "misaligned_fetch", "fault_fetch", @@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } } + if (flags & CPU_DUMP_VU) { + int vlen = cpu->cfg.vlen; + int n_chunk = vlen / 64; + if (vlen == 32) { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]); + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, " %-8s ", + riscv_vr_regnames[i]); + + int vec_reg_offset = i * vlen / 64; + qemu_fprintf(f, "0x"); + for (int j = n_chunk - 1; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64, + env->vreg[vec_reg_offset + j]); + } + qemu_fprintf(f, "\n"); + } + } + } } static void riscv_cpu_set_pc(CPUState *cs, vaddr value)