diff mbox series

[02/12] hw/nvme: remove redundant passing of PCIDevice

Message ID 20220623211821.50534-3-its@irrelevant.dk
State New
Headers show
Series hw/nvme: misc fixes and updates | expand

Commit Message

Klaus Jensen June 23, 2022, 9:18 p.m. UTC 
From: Klaus Jensen <k.jensen@samsung.com>

The NvmeCtrl is a PCIDevice, so remove the redundant passing of the
PCIDevice parameter.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
 hw/nvme/ctrl.c | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index c8c4a0718fc4..b688afccbe5a 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -7007,8 +7007,9 @@  static void nvme_init_state(NvmeCtrl *n)
     }
 }
 
-static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
+static void nvme_init_cmb(NvmeCtrl *n)
 {
+    PCIDevice *pci_dev = PCI_DEVICE(n);
     uint64_t cmb_size = n->params.cmb_size_mb * MiB;
     uint64_t cap = ldq_le_p(&n->bar.cap);
 
@@ -7029,8 +7030,9 @@  static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
     }
 }
 
-static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
+static void nvme_init_pmr(NvmeCtrl *n)
 {
+    PCIDevice *pci_dev = PCI_DEVICE(n);
     uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap);
 
     NVME_PMRCAP_SET_RDS(pmrcap, 1);
@@ -7116,8 +7118,9 @@  static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset)
     return 0;
 }
 
-static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
+static int nvme_init_pci(NvmeCtrl *n, Error **errp)
 {
+    PCIDevice *pci_dev = PCI_DEVICE(n);
     uint8_t *pci_conf = pci_dev->config;
     uint64_t bar_size;
     unsigned msix_table_offset, msix_pba_offset;
@@ -7174,11 +7177,11 @@  static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
     nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize);
 
     if (n->params.cmb_size_mb) {
-        nvme_init_cmb(n, pci_dev);
+        nvme_init_cmb(n);
     }
 
     if (n->pmr.dev) {
-        nvme_init_pmr(n, pci_dev);
+        nvme_init_pmr(n);
     }
 
     if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) {
@@ -7201,8 +7204,9 @@  static void nvme_init_subnqn(NvmeCtrl *n)
     }
 }
 
-static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
+static void nvme_init_ctrl(NvmeCtrl *n)
 {
+    PCIDevice *pci_dev = PCI_DEVICE(n);
     NvmeIdCtrl *id = &n->id_ctrl;
     uint8_t *pci_conf = pci_dev->config;
     uint64_t cap = ldq_le_p(&n->bar.cap);
@@ -7360,10 +7364,11 @@  static void nvme_realize(PCIDevice *pci_dev, Error **errp)
         return;
     }
     nvme_init_state(n);
-    if (nvme_init_pci(n, pci_dev, errp)) {
+    if (nvme_init_pci(n, errp)) {
         return;
     }
-    nvme_init_ctrl(n, pci_dev);
+
+    nvme_init_ctrl(n);
 
     /* setup a namespace if the controller drive property was given */
     if (n->namespace.blkconf.blk) {