From patchwork Mon Jun 20 23:15:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 1645800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20210112.gappssmtp.com header.i=@rivosinc-com.20210112.gappssmtp.com header.a=rsa-sha256 header.s=20210112 header.b=4ZaTTjcr; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LRm843yLNz9sGP for ; Tue, 21 Jun 2022 09:29:40 +1000 (AEST) Received: from localhost ([::1]:56432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3Qpu-0001ll-DX for incoming@patchwork.ozlabs.org; Mon, 20 Jun 2022 19:29:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3QdC-00017m-9R for qemu-devel@nongnu.org; Mon, 20 Jun 2022 19:16:31 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:46681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o3Qd6-0006Ul-UB for qemu-devel@nongnu.org; Mon, 20 Jun 2022 19:16:30 -0400 Received: by mail-pf1-x433.google.com with SMTP id a15so4284825pfv.13 for ; Mon, 20 Jun 2022 16:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CioWz+4k4bNSsvwmzaQvsk4S/oh94GKtuInjXQxKzT8=; b=4ZaTTjcrBPl28jaD+2+EnCsiJTK9on6Zl0xKNtMUvzeLPFsfy2sHwdv1dCa3SIEj4N 3GOps3RCtd0ewpgUBKK5YTzdLXkzcxFufMBk2EQTj3VC+FLrEmn58+lG3lWSxx/7KMzw irt1cjRZ92taJVNfSGBYu1QeD5GFJIMG4O/8h8AcDFwzmInNpnuBqGmRJFSsi0l1kV2i nQsE8VvQPh5z8cHzG08VdQtExQA5B7i1EYqz84O80AJuQG89UyxPxZkcemB+YotZ3Ity kEE5Ilnat305JuRBHhRAl94Vo/DXjqIUuyGv25VThCeHaY2SpGC2c9DlPqzwMefZWTNa y0yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CioWz+4k4bNSsvwmzaQvsk4S/oh94GKtuInjXQxKzT8=; b=2Y6tzkgiV3cVF7W6QHalq6ZSXi609WiSnsatNMLXdVoxjf7a1o4S2LW5XP3TdZ1jd0 yrumfLhW66I087lZ3ynU96ShXAbKQrJpdyg8mO1cS5JDiMfrHlIvdcJ9A7kpimIfbWrq CKPGibSiMRj+O1985XsH7RK/ghFjc1I9jJeOv51vf/xEOu1jymwJOTmFTDbbSWuKmXxl SbC398EvSB2KAuXKx5Yd8gmtqNeXsm6APB3ISuPC/IpLHGLVKA0Uwtuz/3rjaxF0Vr16 +zvO/Sk+27yk98XID0I/MeJviq2wqQQwdG4uT9PUh+OXBYSXnvb6jOkw1XWpHsVuoU7y OYQw== X-Gm-Message-State: AJIora/Kj+XT72h5mkbiBVJ7rEY/ntDDpUfnhP9wO0LJlOVXubSd/z9f JyQw/e0u9cWtRnqfoQB1quoiABQ0X10Dhw== X-Google-Smtp-Source: AGRyM1tGSiaMt0y/92WmWo/2Pg1+4LTiwTBXHInsrG+EVQ1AWlbWbH7q/b5Nn7xA14NNmz8Ygre/2A== X-Received: by 2002:a65:6d0f:0:b0:3fd:8437:c35b with SMTP id bf15-20020a656d0f000000b003fd8437c35bmr22912205pgb.24.1655766983488; Mon, 20 Jun 2022 16:16:23 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id p2-20020a170902a40200b0015e8d4eb285sm9191008plq.207.2022.06.20.16.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jun 2022 16:16:22 -0700 (PDT) From: Atish Patra To: qemu-devel@nongnu.org Cc: Bin Meng , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org, frank.chang@sifive.com Subject: [PATCH v10 09/12] target/riscv: Simplify counter predicate function Date: Mon, 20 Jun 2022 16:15:59 -0700 Message-Id: <20220620231603.2547260-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220620231603.2547260-1-atishp@rivosinc.com> References: <20220620231603.2547260-1-atishp@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng Acked-by: Alistair Francis Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- target/riscv/csr.c | 112 +++++---------------------------------------- 1 file changed, 11 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2664ce265784..9367e2af9b90 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -74,6 +74,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); int ctr_index; + target_ulong ctr_mask; int base_csrno = CSR_CYCLE; bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; @@ -82,122 +83,31 @@ static RISCVException ctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; + ctr_mask = BIT(ctr_index); if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { goto skip_ext_pmu_check; } - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & ctr_mask))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } skip_ext_pmu_check: - if (env->priv == PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if (((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) || + ((env->priv == PRV_U) && (!get_field(env->scounteren, ctr_mask)))) { + return RISCV_EXCP_ILLEGAL_INST; } if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->mcounteren, ctr_mask)) { + /* The bit must be set in mcountern for HS mode access */ + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else if (!get_field(env->hcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif