@@ -295,6 +295,14 @@ static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus)
return R_I2CD_CMD;
}
+static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus)
+{
+ if (aspeed_i2c_is_new_mode(bus->controller)) {
+ return R_I2CS_DEV_ADDR;
+ }
+ return R_I2CD_DEV_ADDR;
+}
+
static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
@@ -83,6 +83,7 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset,
case A_I2CD_AC_TIMING2:
case A_I2CD_INTR_CTRL:
case A_I2CD_INTR_STS:
+ case A_I2CD_DEV_ADDR:
case A_I2CD_POOL_CTRL:
case A_I2CD_BYTE_BUF:
/* Value is already set, don't do anything. */
@@ -720,8 +721,7 @@ static void aspeed_i2c_bus_old_write(AspeedI2CBus *bus, hwaddr offset,
}
break;
case A_I2CD_DEV_ADDR:
- qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
- __func__);
+ bus->regs[R_I2CD_DEV_ADDR] = value;
break;
case A_I2CD_POOL_CTRL:
bus->regs[R_I2CD_POOL_CTRL] &= ~0xffffff;