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[217.237.121.196]) by smtp.gmail.com with ESMTPSA id f25-20020a170906139900b006fe8c831632sm3066160ejc.73.2022.06.03.11.51.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 11:51:11 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , =?utf-8?q?Herv=C3=A9_Poussineau?= , Paolo Bonzini , Bernhard Beschow , Mark Cave-Ayland Subject: [PATCH v4 08/11] hw/isa/piix3: Move pci_map_irq_fn near pci_set_irq_fn Date: Fri, 3 Jun 2022 20:50:42 +0200 Message-Id: <20220603185045.143789-9-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220603185045.143789-1-shentey@gmail.com> References: <20220603185045.143789-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The pci_map_irq_fn was implemented below type_init() which made it inaccessible to QOM functions. So move it up. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index d96ce2b788..c7a9014c3f 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -78,6 +78,17 @@ static void piix3_set_irq(void *opaque, int pirq, int level) piix3_set_irq_level(piix3, pirq, level); } +/* + * Return the global irq number corresponding to a given device irq + * pin. We could also use the bus number to have a more precise mapping. + */ +static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) +{ + int slot_addend; + slot_addend = PCI_SLOT(pci_dev->devfn) - 1; + return (pci_intx + slot_addend) & 3; +} + static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin) { PIIX3State *piix3 = opaque; @@ -350,17 +361,6 @@ static void piix3_register_types(void) type_init(piix3_register_types) -/* - * Return the global irq number corresponding to a given device irq - * pin. We could also use the bus number to have a more precise mapping. - */ -static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) -{ - int slot_addend; - slot_addend = PCI_SLOT(pci_dev->devfn) - 1; - return (pci_intx + slot_addend) & 3; -} - PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus) { PIIX3State *piix3;