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[78.54.75.232]) by smtp.gmail.com with ESMTPSA id w4-20020a170907270400b006f3ef214e22sm5418768ejk.136.2022.05.22.14.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 May 2022 14:25:04 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH v2 5/6] hw/isa/piix4: QOM'ify PIIX4 PM creation Date: Sun, 22 May 2022 23:24:30 +0200 Message-Id: <20220522212431.14598-6-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220522212431.14598-1-shentey@gmail.com> References: <20220522212431.14598-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Just like the real hardware, create the PIIX4 ACPI controller as part of the PIIX4 southbridge. This also mirrors how the IDE and USB functions are already created. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 14 +++++++------- hw/mips/malta.c | 3 ++- include/hw/southbridge/piix.h | 2 +- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4968c69da9..1645f63450 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -206,6 +206,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) PIIX4State *s = PIIX4_PCI_DEVICE(dev); PCIDevice *pci; PCIBus *pci_bus = pci_get_bus(dev); + I2CBus *smbus; ISABus *isa_bus; qemu_irq *i8259_out_irq; @@ -252,6 +253,11 @@ static void piix4_realize(PCIDevice *dev, Error **errp) /* USB */ pci_create_simple(pci_bus, dev->devfn + 2, "piix4-usb-uhci"); + /* ACPI controller */ + smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100, s->isa[9], + NULL, 0, NULL); + object_property_add_const_link(OBJECT(s), "smbus", OBJECT(smbus)); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); } @@ -301,7 +307,7 @@ static void piix4_register_types(void) type_init(piix4_register_types) -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus) +DeviceState *piix4_create(PCIBus *pci_bus) { PCIDevice *pci; DeviceState *dev; @@ -311,11 +317,5 @@ DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus) TYPE_PIIX4_PCI_DEVICE); dev = DEVICE(pci); - if (smbus) { - *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0, NULL); - } - return dev; } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e446b25ad0..b0fc84ccbb 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1399,8 +1399,9 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - dev = piix4_create(pci_bus, &smbus); + dev = piix4_create(pci_bus); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + smbus = I2C_BUS(qdev_get_child_bus(dev, "smbus")); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 0bec7f8ca3..2c21359efa 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -76,6 +76,6 @@ DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, PIIX3State *piix3_create(PCIBus *pci_bus); -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus); +DeviceState *piix4_create(PCIBus *pci_bus); #endif