diff mbox series

[RFC,2/4] tcg/ppc: ST_ST memory ordering is not provided with eieio

Message ID 20220503103334.2046414-2-npiggin@gmail.com
State New
Headers show
Series [RFC,1/4] target/ppc: Fix eieio memory ordering semantics | expand

Commit Message

Nicholas Piggin May 3, 2022, 10:33 a.m. UTC 
eieio does not provide ordering between stores to CI memory and stores
to cacheable memory so it can't be used as a general ST_ST barrier.

Signed-of-by: Nicholas Piggin <npiggin@gmail.com>
---
 tcg/ppc/tcg-target.c.inc | 2 --
 1 file changed, 2 deletions(-)

Comments

Richard Henderson May 3, 2022, 3:01 p.m. UTC | #1 
On 5/3/22 03:33, Nicholas Piggin wrote:
> eieio does not provide ordering between stores to CI memory and stores
> to cacheable memory so it can't be used as a general ST_ST barrier.
> 
> Signed-of-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>   tcg/ppc/tcg-target.c.inc | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index cfcd121f9c..3ff845d063 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -1836,8 +1836,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
>       a0 &= TCG_MO_ALL;
>       if (a0 == TCG_MO_LD_LD) {
>           insn = LWSYNC;
> -    } else if (a0 == TCG_MO_ST_ST) {
> -        insn = EIEIO;
>       }
>       tcg_out32(s, insn);
>   }

Certainly matches the comment from patch 1.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index cfcd121f9c..3ff845d063 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1836,8 +1836,6 @@  static void tcg_out_mb(TCGContext *s, TCGArg a0)
     a0 &= TCG_MO_ALL;
     if (a0 == TCG_MO_LD_LD) {
         insn = LWSYNC;
-    } else if (a0 == TCG_MO_ST_ST) {
-        insn = EIEIO;
     }
     tcg_out32(s, insn);
 }