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Received: from 35.201.90.79.rev.sfr.net ([79.90.201.35]:39314 helo=palmier.u-ga.fr) by hp220.hostpapa.com with esmtpa (Exim 4.94.2) (envelope-from ) id 1nd7fv-000ltT-3q; Sat, 09 Apr 2022 11:46:32 +0200 From: =?utf-8?b?RnLDqWTDqXJpYyBQw6l0cm90?= To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] target/riscv: replace TARGET_LONG_BITS in gdbstub Date: Sat, 9 Apr 2022 11:46:11 +0200 Message-Id: <20220409094612.1908512-2-frederic.petrot@univ-grenoble-alpes.fr> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220409094612.1908512-1-frederic.petrot@univ-grenoble-alpes.fr> References: <20220409094612.1908512-1-frederic.petrot@univ-grenoble-alpes.fr> MIME-Version: 1.0 X-AuthUser: frederic@petrot.fr Received-SPF: neutral client-ip=23.83.209.62; envelope-from=frederic.petrot@univ-grenoble-alpes.fr; helo=fossa.birch.relay.mailchannels.net X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, =?utf-8?b?RnLDqWTDqXJpYyBQw6l0cm90?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that we have misa xlen, use that in riscv gdbstub.c instead of the TARGET_LONG_BITS define, and use riscv_cpu_mxl_bits to provide the number of bits in a consistent way. Signed-off-by: Frédéric Pétrot --- target/riscv/gdbstub.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 9ed049c29e..1602f76d2b 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -305,7 +305,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) CPURISCVState *env = &cpu->env; GString *s = g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize = 16 << env->misa_mxl_max; + int bitsize = riscv_cpu_mxl_bits(env); int i; /* Until gdb knows about 128-bit registers */ @@ -385,10 +385,11 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) for (i = 0; i < 7; i++) { g_string_append_printf(s, - "", - vector_csrs[i], TARGET_LONG_BITS, base_reg++); + vector_csrs[i], riscv_cpu_mxl_bits(&cpu->env), + base_reg++); num_regs++; }