From patchwork Thu Mar 31 08:15:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jamin Lin X-Patchwork-Id: 1611615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4KTbtx0w4Cz9sGD for ; Thu, 31 Mar 2022 19:24:23 +1100 (AEDT) Received: from localhost ([::1]:60930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZq6O-0007Uf-6g for incoming@patchwork.ozlabs.org; Thu, 31 Mar 2022 04:24:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:57110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZpz7-0001Vy-BA; Thu, 31 Mar 2022 04:16:49 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:41430) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZpz5-0000ib-0m; Thu, 31 Mar 2022 04:16:49 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 22V84omw054244; Thu, 31 Mar 2022 16:04:50 +0800 (GMT-8) (envelope-from jamin_lin@aspeedtech.com) Received: from localhost.localdomain (192.168.70.87) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 31 Mar 2022 16:15:48 +0800 From: Jamin Lin To: Alistair Francis , Peter Maydell , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Andrew Jeffery , Joel Stanley , Cleber Rosa , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Wainer dos Santos Moschetta" , Beraldo Leal , "open list:STM32F205" , "open list:All patches CC here" Subject: [PATCH v2 2/9] aspeed/smc: Add AST1030 support Date: Thu, 31 Mar 2022 16:15:38 +0800 Message-ID: <20220331081545.7140-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220331081545.7140-1-jamin_lin@aspeedtech.com> References: <20220331081545.7140-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.70.87] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 22V84omw054244 Received-SPF: pass client-ip=211.20.114.71; envelope-from=jamin_lin@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Steven Lee AST1030 spi controller's address decoding unit is 1MB that is identical to ast2600, but fmc address decoding unit is 512kb. Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller. In addition, add ast1030 fmc, spi1, and spi2 class init handler. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 160 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 48305e1574..81af783729 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1696,6 +1696,163 @@ static const TypeInfo aspeed_2600_spi2_info = { .class_init = aspeed_2600_spi2_class_init, }; +/* + * The FMC Segment Registers of the AST1030 have a 512KB unit. + * Only bits [27:19] are used for decoding. + */ +#define AST1030_SEG_ADDR_MASK 0x0ff80000 + +static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, + const AspeedSegments *seg) +{ + uint32_t reg = 0; + + /* Disabled segments have a nil register */ + if (!seg->size) { + return 0; + } + + reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ + reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ + return reg; +} + +static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, + uint32_t reg, AspeedSegments *seg) +{ + uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK; + uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK; + AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); + + if (reg) { + seg->addr = asc->flash_window_base + start_offset; + seg->size = end_offset + (512 * KiB) - start_offset; + } else { + seg->addr = asc->flash_window_base; + seg->size = 0; + } +} + +static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = { + [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), +}; + +static const AspeedSegments aspeed_1030_fmc_segments[] = { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); + + dc->desc = "Aspeed 1030 FMC Controller"; + asc->r_conf = R_CONF; + asc->r_ce_ctrl = R_CE_CTRL; + asc->r_ctrl0 = R_CTRL0; + asc->r_timings = R_TIMINGS; + asc->nregs_timings = 2; + asc->conf_enable_w0 = CONF_ENABLE_W0; + asc->cs_num_max = 2; + asc->segments = aspeed_1030_fmc_segments; + asc->segment_addr_mask = 0x0ff80ff8; + asc->resets = aspeed_1030_fmc_resets; + asc->flash_window_base = 0x80000000; + asc->flash_window_size = 0x10000000; + asc->features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_WDT_CONTROL; + asc->dma_flash_mask = 0x0FFFFFFC; + asc->dma_dram_mask = 0x000BFFFC; + asc->nregs = ASPEED_SMC_R_MAX; + asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; + asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_fmc_info = { + .name = "aspeed.fmc-ast1030", + .parent = TYPE_ASPEED_SMC, + .class_init = aspeed_1030_fmc_class_init, +}; + +static const AspeedSegments aspeed_1030_spi1_segments[] = { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); + + dc->desc = "Aspeed 1030 SPI1 Controller"; + asc->r_conf = R_CONF; + asc->r_ce_ctrl = R_CE_CTRL; + asc->r_ctrl0 = R_CTRL0; + asc->r_timings = R_TIMINGS; + asc->nregs_timings = 2; + asc->conf_enable_w0 = CONF_ENABLE_W0; + asc->cs_num_max = 2; + asc->segments = aspeed_1030_spi1_segments; + asc->segment_addr_mask = 0x0ff00ff0; + asc->flash_window_base = 0x90000000; + asc->flash_window_size = 0x10000000; + asc->features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_WDT_CONTROL; + asc->dma_flash_mask = 0x0FFFFFFC; + asc->dma_dram_mask = 0x000BFFFC; + asc->nregs = ASPEED_SMC_R_MAX; + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_spi1_info = { + .name = "aspeed.spi1-ast1030", + .parent = TYPE_ASPEED_SMC, + .class_init = aspeed_1030_spi1_class_init, +}; +static const AspeedSegments aspeed_1030_spi2_segments[] = { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); + + dc->desc = "Aspeed 1030 SPI2 Controller"; + asc->r_conf = R_CONF; + asc->r_ce_ctrl = R_CE_CTRL; + asc->r_ctrl0 = R_CTRL0; + asc->r_timings = R_TIMINGS; + asc->nregs_timings = 2; + asc->conf_enable_w0 = CONF_ENABLE_W0; + asc->cs_num_max = 2; + asc->segments = aspeed_1030_spi2_segments; + asc->segment_addr_mask = 0x0ff00ff0; + asc->flash_window_base = 0xb0000000; + asc->flash_window_size = 0x10000000; + asc->features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_WDT_CONTROL; + asc->dma_flash_mask = 0x0FFFFFFC; + asc->dma_dram_mask = 0x000BFFFC; + asc->nregs = ASPEED_SMC_R_MAX; + asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; + asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; + asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_spi2_info = { + .name = "aspeed.spi2-ast1030", + .parent = TYPE_ASPEED_SMC, + .class_init = aspeed_1030_spi2_class_init, +}; + static void aspeed_smc_register_types(void) { type_register_static(&aspeed_smc_flash_info); @@ -1709,6 +1866,9 @@ static void aspeed_smc_register_types(void) type_register_static(&aspeed_2600_fmc_info); type_register_static(&aspeed_2600_spi1_info); type_register_static(&aspeed_2600_spi2_info); + type_register_static(&aspeed_1030_fmc_info); + type_register_static(&aspeed_1030_spi1_info); + type_register_static(&aspeed_1030_spi2_info); } type_init(aspeed_smc_register_types)