@@ -75,6 +75,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
!RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ return smstateen_acc_ok(env, PRV_U, SMSTATEEN0_FCSR);
+ }
#endif
return RISCV_EXCP_NONE;
}
@@ -2006,6 +2010,10 @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno,
(1UL << SMSTATEEN0_HSENVCFG);
reg = &env->mstateen[csrno - CSR_MSTATEEN0];
+ if (riscv_has_ext(env, RVF)) {
+ wr_mask |= 1UL << SMSTATEEN0_FCSR;
+ }
+
write_smstateen(env, reg, wr_mask, new_val);
return RISCV_EXCP_NONE;
@@ -2030,6 +2038,10 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
reg = &env->mstateen[csrno - CSR_MSTATEEN0H - 0x10];
val = (uint64_t)new_val << 32;
val |= *reg & 0xFFFFFFFF;
+ if (riscv_has_ext(env, RVF)) {
+ wr_mask |= 1UL << SMSTATEEN0_FCSR;
+ }
+
write_smstateen(env, reg, wr_mask, val);
return RISCV_EXCP_NONE;
@@ -2051,6 +2063,10 @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno,
(1UL << SMSTATEEN0_HSENVCFG);
int index = csrno - CSR_HSTATEEN0;
+ if (riscv_has_ext(env, RVF)) {
+ wr_mask |= 1UL << SMSTATEEN0_FCSR;
+ }
+
reg = &env->hstateen[index];
wr_mask &= env->mstateen[index];
write_smstateen(env, reg, wr_mask, new_val);
@@ -2075,6 +2091,10 @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno,
uint64_t wr_mask = (1UL << SMSTATEEN_STATEN) |
(1UL << SMSTATEEN0_HSENVCFG);
+ if (riscv_has_ext(env, RVF)) {
+ wr_mask |= 1UL << SMSTATEEN0_FCSR;
+ }
+
reg = &env->hstateen[index];
val = (uint64_t)new_val << 32;
val |= *reg & 0xFFFFFFFF;
@@ -2100,6 +2120,10 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno,
int index = csrno - CSR_SSTATEEN0;
bool virt = riscv_cpu_virt_enabled(env);
+ if (riscv_has_ext(env, RVF)) {
+ wr_mask |= 1UL << SMSTATEEN0_FCSR;
+ }
+
reg = &env->sstateen[index];
if (virt) {
wr_mask &= env->mstateen[index];
If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- target/riscv/csr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)