@@ -49,6 +49,29 @@ typedef struct Or1ksimState {
} Or1ksimState;
+enum {
+ OR1KSIM_DRAM,
+ OR1KSIM_UART,
+ OR1KSIM_ETHOC,
+ OR1KSIM_OMPIC,
+};
+
+enum {
+ OR1KSIM_OMPIC_IRQ = 1,
+ OR1KSIM_UART_IRQ = 2,
+ OR1KSIM_ETHOC_IRQ = 4,
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} or1ksim_memmap[] = {
+ [OR1KSIM_DRAM] = { 0x00000000, 0 },
+ [OR1KSIM_UART] = { 0x90000000, 0x100 },
+ [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
+ [OR1KSIM_OMPIC] = { 0x98000000, 16 },
+};
+
static struct openrisc_boot_info {
uint32_t bootstrap_pc;
} boot_info;
@@ -176,21 +199,24 @@ static void openrisc_sim_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0, ram);
if (nd_table[0].used) {
- openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
- cpus, 4, nd_table);
+ openrisc_sim_net_init(or1ksim_memmap[OR1KSIM_ETHOC].base,
+ or1ksim_memmap[OR1KSIM_ETHOC].base + 0x400,
+ smp_cpus, cpus,
+ OR1KSIM_ETHOC_IRQ, nd_table);
}
if (smp_cpus > 1) {
- openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);
+ openrisc_sim_ompic_init(or1ksim_memmap[OR1KSIM_OMPIC].base, smp_cpus,
+ cpus, OR1KSIM_OMPIC_IRQ);
- serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),
- get_cpu_irq(cpus, 1, 2));
+ serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, OR1KSIM_UART_IRQ),
+ get_cpu_irq(cpus, 1, OR1KSIM_UART_IRQ));
} else {
- serial_irq = get_cpu_irq(cpus, 0, 2);
+ serial_irq = get_cpu_irq(cpus, 0, OR1KSIM_UART_IRQ);
}
- serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_mm_init(get_system_memory(), or1ksim_memmap[OR1KSIM_UART].base, 0,
+ serial_irq, 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
openrisc_load_kernel(ram_size, kernel_filename);
}