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[78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:46:02 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants Date: Wed, 16 Feb 2022 23:45:18 +0100 Message-Id: <20220216224519.157233-7-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Herv=C3=A9_Poussineau?= , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a follow-up on patch "malta: Move PCI interrupt handling from gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably didn't want to use piix4-specific constants. Now that the interrupt handing resides in piix4, its constants can be used. Signed-off-by: Bernhard Beschow Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 2e9b5ccada..f876c71750 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -61,10 +61,10 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < 16) { + if (pic_irq < ISA_NUM_IRQS) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; - for (i = 0; i < 4; i++) { + for (i = 0; i < PIIX_NUM_PIRQS; i++) { if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { pic_level |= pci_bus_get_irq_level(bus, i); } @@ -315,7 +315,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS); return dev; }