Message ID | 20220216224519.157233-6-shentey@gmail.com |
---|---|
State | New |
Headers | show |
Series | malta: Fix PCI IRQ levels to be preserved during migration, cleanup | expand |
On Wed, Feb 16, 2022 at 11:45:17PM +0100, Bernhard Beschow wrote: > Now that piix4_set_irq's opaque parameter references own PIIX4State, > piix4_dev becomes redundant. > > Signed-off-by: Bernhard Beschow <shentey@gmail.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> > --- > hw/isa/piix4.c | 10 +++------- > include/hw/southbridge/piix.h | 2 -- > 2 files changed, 3 insertions(+), 9 deletions(-) > > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c > index caa2002e2c..2e9b5ccada 100644 > --- a/hw/isa/piix4.c > +++ b/hw/isa/piix4.c > @@ -39,8 +39,6 @@ > #include "sysemu/runstate.h" > #include "qom/object.h" > > -PCIDevice *piix4_dev; > - > struct PIIX4State { > PCIDevice dev; > qemu_irq cpu_intr; > @@ -58,16 +56,16 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) > { > int i, pic_irq, pic_level; > PIIX4State *s = opaque; > - PCIBus *bus = pci_get_bus(piix4_dev); > + PCIBus *bus = pci_get_bus(&s->dev); > > /* now we change the pic irq level according to the piix irq mappings */ > /* XXX: optimize */ > - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; > + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; > if (pic_irq < 16) { > /* The pic level is the logical OR of all the PCI irqs mapped to it. */ > pic_level = 0; > for (i = 0; i < 4; i++) { > - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { > + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { > pic_level |= pci_bus_get_irq_level(bus, i); > } > } > @@ -219,8 +217,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) > return; > } > isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); > - > - piix4_dev = dev; > } > > static void piix4_init(Object *obj) > diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h > index 6387f2b612..f63f83e5c6 100644 > --- a/include/hw/southbridge/piix.h > +++ b/include/hw/southbridge/piix.h > @@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State; > DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, > TYPE_PIIX3_PCI_DEVICE) > > -extern PCIDevice *piix4_dev; > - > PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); > > DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); > -- > 2.35.1
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index caa2002e2c..2e9b5ccada 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -39,8 +39,6 @@ #include "sysemu/runstate.h" #include "qom/object.h" -PCIDevice *piix4_dev; - struct PIIX4State { PCIDevice dev; qemu_irq cpu_intr; @@ -58,16 +56,16 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; PIIX4State *s = opaque; - PCIBus *bus = pci_get_bus(piix4_dev); + PCIBus *bus = pci_get_bus(&s->dev); /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { pic_level |= pci_bus_get_irq_level(bus, i); } } @@ -219,8 +217,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); - - piix4_dev = dev; } static void piix4_init(Object *obj) diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index 6387f2b612..f63f83e5c6 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State; DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, TYPE_PIIX3_PCI_DEVICE) -extern PCIDevice *piix4_dev; - PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);