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[78.54.75.152]) by smtp.gmail.com with ESMTPSA id t26sm1475820edv.50.2022.02.16.14.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Feb 2022 14:45:59 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Subject: [PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() Date: Wed, 16 Feb 2022 23:45:16 +0100 Message-Id: <20220216224519.157233-5-shentey@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220216224519.157233-1-shentey@gmail.com> References: <20220216224519.157233-1-shentey@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::62e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.978, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Bernhard Beschow , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Herv=C3=A9_Poussineau?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Passing PIIX4State rather than just the qemu_irq allows for resolving the global piix4_dev variable. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin --- hw/isa/piix4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 179968b18e..caa2002e2c 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -57,7 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE) static void piix4_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; - qemu_irq *pic = opaque; + PIIX4State *s = opaque; PCIBus *bus = pci_get_bus(piix4_dev); /* now we change the pic irq level according to the piix irq mappings */ @@ -71,7 +71,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) pic_level |= pci_bus_get_irq_level(bus, i); } } - qemu_set_irq(pic[pic_irq], pic_level); + qemu_set_irq(s->isa[pic_irq], pic_level); } } @@ -319,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) NULL, 0, NULL); } - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4); + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4); return dev; }