[v3,2/2] This patch includes i3c instance in ast2600 soc.

v3:
- Remove unrelated changes to SPI2 address
- Remove controller irq line

v2: Rebase to mainline QEMU

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
---
 hw/arm/aspeed_ast2600.c     | 16 ++++++++++++++++
 include/hw/arm/aspeed_soc.h |  3 +++
 2 files changed, 19 insertions(+)

On 1/11/22 09:45, Troy Lee wrote:
> v3:
> - Remove unrelated changes to SPI2 address
> - Remove controller irq line
> 
> v2: Rebase to mainline QEMU
> 
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

You should consider updating the documentation :

   https://qemu.readthedocs.io/en/latest/system/arm/aspeed.html

Thanks,

C.

> ---
>   hw/arm/aspeed_ast2600.c     | 16 ++++++++++++++++
>   include/hw/arm/aspeed_soc.h |  3 +++
>   2 files changed, 19 insertions(+)
> 
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index e33483fb5d..8f37bdb1d8 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -61,6 +61,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
>       [ASPEED_DEV_UART1]     = 0x1E783000,
>       [ASPEED_DEV_UART5]     = 0x1E784000,
>       [ASPEED_DEV_VUART]     = 0x1E787000,
> +    [ASPEED_DEV_I3C]       = 0x1E7A0000,
>       [ASPEED_DEV_SDRAM]     = 0x80000000,
>   };
>   
> @@ -108,6 +109,7 @@ static const int aspeed_soc_ast2600_irqmap[] = {
>       [ASPEED_DEV_ETH4]      = 33,
>       [ASPEED_DEV_KCS]       = 138,   /* 138 -> 142 */
>       [ASPEED_DEV_DP]        = 62,
> +    [ASPEED_DEV_I3C]       = 102,   /* 102 -> 107 */
>   };
>   
>   static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
> @@ -223,6 +225,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
>   
>       snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
>       object_initialize_child(obj, "hace", &s->hace, typename);
> +
> +    object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
>   }
>   
>   /*
> @@ -523,6 +527,18 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>       sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]);
>       sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
>                          aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
> +
> +    /* I3C */
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
> +    for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
> +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
> +                                        sc->irqmap[ASPEED_DEV_I3C] + i);
> +        /* The AST2600 I3C controller has one IRQ per bus. */
> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
> +    }
>   }
>   
>   static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 18fb7eed46..cae9906684 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -21,6 +21,7 @@
>   #include "hw/timer/aspeed_timer.h"
>   #include "hw/rtc/aspeed_rtc.h"
>   #include "hw/i2c/aspeed_i2c.h"
> +#include "hw/misc/aspeed_i3c.h"
>   #include "hw/ssi/aspeed_smc.h"
>   #include "hw/misc/aspeed_hace.h"
>   #include "hw/watchdog/wdt_aspeed.h"
> @@ -51,6 +52,7 @@ struct AspeedSoCState {
>       AspeedRtcState rtc;
>       AspeedTimerCtrlState timerctrl;
>       AspeedI2CState i2c;
> +    AspeedI3CState i3c;
>       AspeedSCUState scu;
>       AspeedHACEState hace;
>       AspeedXDMAState xdma;
> @@ -141,6 +143,7 @@ enum {
>       ASPEED_DEV_HACE,
>       ASPEED_DEV_DPMCU,
>       ASPEED_DEV_DP,
> +    ASPEED_DEV_I3C,
>   };
>   
>   #endif /* ASPEED_SOC_H */
>

On Tue, 11 Jan 2022 at 08:46, Troy Lee <troy_lee@aspeedtech.com> wrote:
>
> v3:
> - Remove unrelated changes to SPI2 address
> - Remove controller irq line
>
> v2: Rebase to mainline QEMU
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>

This turns out not to build on macOS or on 32-bit hosts
because of format string issues -- you can't portably
use %lx to print uint64_t or hwaddr types. I have folded
in the following fix:

diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c
index 43771d768ad..f54f5da522b 100644
--- a/hw/misc/aspeed_i3c.c
+++ b/hw/misc/aspeed_i3c.c
@@ -150,7 +150,8 @@ static void aspeed_i3c_device_write(void *opaque,
hwaddr offset,
     case R_I3C_VER_TYPE:
     case R_EXTENDED_CAPABILITY:
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: write to readonly register[%02lx] = %08lx\n",
+                      "%s: write to readonly register[0x%02" HWADDR_PRIx
+                      "] = 0x%08" PRIx64 "\n",
                       __func__, offset, value);
         break;
     case R_RX_TX_DATA_PORT:
@@ -231,13 +232,15 @@ static void aspeed_i3c_write(void *opaque,
     case R_I3C6_REG1:
         if (data & R_I3C1_REG1_I2C_MODE_MASK) {
             qemu_log_mask(LOG_UNIMP,
-                          "%s: Not support I2C mode [%08lx]=%08lx",
+                          "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx
+                          "]=%08" PRIx64 "\n",
                           __func__, addr << 2, data);
             break;
         }
         if (data & R_I3C1_REG1_SA_EN_MASK) {
             qemu_log_mask(LOG_UNIMP,
-                          "%s: Not support slave mode [%08lx]=%08lx",
+                          "%s: Unsupported slave mode [%08" HWADDR_PRIx
+                          "]=0x%08" PRIx64 "\n",
                           __func__, addr << 2, data);
             break;
         }

which also includes a small grammar fix, adds the missing
trailing newlines, and includes the "0x" prefix to make it
clearer to the user that the values printed are hex.

thanks
-- PMM