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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id h2sm179293lji.50.2022.01.06.05.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jan 2022 05:40:24 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH] target/riscv: Fix position of 'experimental' comment Date: Thu, 6 Jan 2022 14:40:20 +0100 Message-Id: <20220106134020.1628889-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::233 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x233.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Vineet Gupta , Philipp Tomsich , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When commit 0643c12e4b dropped the 'x-' prefix for Zb[abcs] and set them to be enabled by default, the comment about experimental extensions was kept in place above them. This moves it down a few lines to only cover experimental extensions. References: 0643c12e4b ("target/riscv: Enable bitmanip Zb[abcs] instructions") Signed-off-by: Philipp Tomsich Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..e322e729d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -640,11 +640,12 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */