@@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
@@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
return do_csrw(ctx, a->csr, src);
}
- TCGv mask = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
@@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
{
- RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
+ target_ulong mask = cpu_get_xl(env) == MXL_RV32 ? UINT32_MAX : -1;
+ RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
if (ret != RISCV_EXCP_NONE) {
riscv_raise_exception(env, ret, GETPC());
Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/op_helper.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-)