Message ID | 20211111055800.42672-17-zhiwei_liu@c-sky.com |
---|---|
State | New |
Headers | show |
Series | Support UXL filed in xstatus | expand |
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f5aabd5263..41c7c88904 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a) (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && + /* TODO: RV128 could allow 128-bit atomics */ + ((1 << s->sew) <= (get_xl(s) == MXL_RV32 ? 4 : 8)) && ((1 << s->sew) >= 4)); }