| Message ID | 20211019094812.614056-7-frederic.petrot@univ-grenoble-alpes.fr |
|---|---|
| State | New |
| Headers | show |
| Series | Adding partial support for 128-bit riscv target | expand |
On 10/19/21 2:47 AM, Frédéric Pétrot wrote: > The upper 64-bit of the 128-bit registers have now a place inside > the cpu state structure, and are created as globals for future use. > > Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> > Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> > --- > target/riscv/cpu.h | 1 + > target/riscv/translate.c | 5 ++++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c24bc9a039..c8b98f1b70 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) > > struct CPURISCVState { > target_ulong gpr[32]; > + target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ At first I was going to suggest that the 128-bit value be represented in host byte order, but then I thought that would just get in the way until such any such host operations are apparent. You are missing an update to machine.c for migration (and probably more importantly, loadvm/savevm for debugging). I think you'll want to put these into a separate subsection, controlled by misa_mxl_max == RV128. > for (i = 1; i < 32; i++) { > cpu_gpr[i] = tcg_global_mem_new(cpu_env, > offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); > + cpu_gprh[i] = tcg_global_mem_new(cpu_env, > + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]); This will just be confusing in the tcg dumps -- let's not name the two temps the identically. Honestly, I'm not 100% thrilled about the / that appears in the current name; I think it would be easiest to do g_string_printf("x%d", i) and g_string_printf("x%dh", i) r~
Le 20/10/2021 à 16:44, Richard Henderson a écrit : > On 10/19/21 2:47 AM, Frédéric Pétrot wrote: >> The upper 64-bit of the 128-bit registers have now a place inside >> the cpu state structure, and are created as globals for future use. >> >> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> >> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> >> --- >> target/riscv/translate.c | 5 ++++- >> 2 files changed, 5 insertions(+), 1 deletion(-) >> for (i = 1; i < 32; i++) { >> cpu_gpr[i] = tcg_global_mem_new(cpu_env, >> offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); >> + cpu_gprh[i] = tcg_global_mem_new(cpu_env, >> + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]); > > This will just be confusing in the tcg dumps -- let's not name the two temps the > identically. Agreed. > Honestly, I'm not 100% thrilled about the / that appears in the current name; I > think it would be easiest to do > > g_string_printf("x%d", i) > and > g_string_printf("x%dh", i) Registers sw names are used by gcc -S and the default objdump -d output, and also by disas/riscv.c, so dropping them might be a bit rough. For now I'll just add an h in the existing names, and suggest we wait to see if anyone cares. Frédéric
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c24bc9a039..c8b98f1b70 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -109,6 +109,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { target_ulong gpr[32]; + target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ /* vector coprocessor state. */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3c2e9fb790..b64fe8470d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -32,7 +32,7 @@ #include "instmap.h" /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -755,10 +755,13 @@ void riscv_translate_init(void) * unless you specifically block reads/writes to reg 0. */ cpu_gpr[0] = NULL; + cpu_gprh[0] = NULL; for (i = 1; i < 32; i++) { cpu_gpr[i] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + cpu_gprh[i] = tcg_global_mem_new(cpu_env, + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]); } for (i = 0; i < 32; i++) {
The upper 64-bit of the 128-bit registers have now a place inside the cpu state structure, and are created as globals for future use. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> --- target/riscv/cpu.h | 1 + target/riscv/translate.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-)