diff mbox series

[v2,22/27] target/riscv: adding high part of some csrs

Message ID 20211006212833.108706-23-frederic.petrot@univ-grenoble-alpes.fr
State New
Headers show
Series Adding partial support for 128-bit riscv target | expand

Commit Message

Frédéric Pétrot Oct. 6, 2021, 9:28 p.m. UTC 
Adding the high part of a minimal set of csr.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
 target/riscv/cpu.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 81cbd77d09..a2d7d65efb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -196,9 +196,14 @@  struct CPURISCVState {
     target_ulong hgatp;
     uint64_t htimedelta;
 
-    /* Upper 64-bits of 128-bit misa CSR */
+    /* Upper 64-bits of 128-bit CSRs */
     uint64_t misah;
     uint64_t misah_mask;
+    uint64_t mtvech;
+    uint64_t mscratchh;
+    uint64_t mepch;
+    uint64_t satph;
+    uint64_t mstatush;
 
     /* Virtual CSRs */
     /*