diff mbox series

[v2,10/27] target/riscv: adding accessors to the registers upper part

Message ID 20211006212833.108706-11-frederic.petrot@univ-grenoble-alpes.fr
State New
Headers show
Series Adding partial support for 128-bit riscv target | expand

Commit Message

Frédéric Pétrot Oct. 6, 2021, 9:28 p.m. UTC 
Set and get functions to access the 64 top bits of the register, stored
in the gprh field of the cpu state.
It looks as if the access to the gprh field can not be protected to make
sure it is accessed only in the 128-bit version of the processor because
the misa/misah field is writable (as it should since the spec indicates
that the registers size might be dynamically changeable), although it is
for now only set at initialization time.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
 target/riscv/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0700c82a36..9a74abecdd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -251,6 +251,25 @@  static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
     g_assert_not_reached();
 }
 
+/* Make sure high part of registers not accessed when not 128-bit */
+static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
+{
+    if (is_128bit(ctx)) {
+        return cpu_gprh[reg_num];
+    } else {
+        /* Cannot use qemu_build_not_reached as misa is rw */
+        return 0;
+    }
+}
+
+static TCGv get_gprh(DisasContext *ctx, int reg_num)
+{
+    if (reg_num == 0 || ctx->w) {
+        return ctx->zero;
+    }
+    return cpu_gprh_check(ctx, reg_num);
+}
+
 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 {
     if (reg_num == 0 || ctx->w) {
@@ -259,6 +278,14 @@  static TCGv dest_gpr(DisasContext *ctx, int reg_num)
     return cpu_gpr[reg_num];
 }
 
+static TCGv dest_gprh(DisasContext *ctx, int reg_num)
+{
+    if (reg_num == 0 || ctx->w) {
+        return temp_new(ctx);
+    }
+    return cpu_gprh_check(ctx, reg_num);
+}
+
 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 {
     if (reg_num != 0) {
@@ -270,6 +297,17 @@  static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
     }
 }
 
+static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
+{
+    if (reg_num != 0) {
+        if (ctx->w) {
+            tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num], 63);
+        } else {
+            tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
+        }
+    }
+}
+
 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 {
     target_ulong next_pc;
@@ -404,6 +442,13 @@  static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
 
     gen_set_gpr(ctx, a->rd, dest);
 
+    /* Temporary code so that the patch compiles */
+    if (is_128bit(ctx)) {
+        (void)get_gprh(ctx, 6);
+        (void)dest_gprh(ctx, 6);
+        gen_set_gprh(ctx, 6, NULL);
+    }
+
     return true;
 }