From patchwork Tue Oct 5 05:26:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Delevoryas X-Patchwork-Id: 1536480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: bilbo.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=fb.com header.i=@fb.com header.a=rsa-sha256 header.s=facebook header.b=S7giCBYR; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HNmNr3zF3z9sRK for ; Tue, 5 Oct 2021 16:29:32 +1100 (AEDT) Received: from localhost ([::1]:60968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mXd17-0005th-Ho for incoming@patchwork.ozlabs.org; Tue, 05 Oct 2021 01:29:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38902) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXd0L-0005rk-6J for qemu-devel@nongnu.org; Tue, 05 Oct 2021 01:28:41 -0400 Received: from mx0b-00082601.pphosted.com ([67.231.153.30]:63738 helo=mx0a-00082601.pphosted.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mXd0I-00021F-P1 for qemu-devel@nongnu.org; Tue, 05 Oct 2021 01:28:40 -0400 Received: from pps.filterd (m0089730.ppops.net [127.0.0.1]) by m0089730.ppops.net (8.16.1.2/8.16.1.2) with SMTP id 1953j9Z0030229 for ; Mon, 4 Oct 2021 22:28:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fb.com; h=from : to : cc : subject : date : message-id : content-type : content-transfer-encoding : mime-version; s=facebook; bh=fugQ0CzHB1aOiTbKa2/YI88w0TtcR7Uc8sV19lZ7Qps=; b=S7giCBYRcLXQBiCgBHttDk2un45Ke4FaZfxF+GTLR0k1MEdIeRYGoCMRMprAxb4oJHu8 SV5IOB2guV+YkFkPyT+cC7kzhrkhBhlQ+mQmsUoBNkAYwJv4Lce/owHS7ZKnRQ1DISpo jlmjok84W5k5otkcZOs31EHkak52nHICRHY= Received: from mail.thefacebook.com ([163.114.132.120]) by m0089730.ppops.net with ESMTP id 3bg9jbap5b-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Mon, 04 Oct 2021 22:28:37 -0700 Received: from intmgw001.46.prn1.facebook.com (2620:10d:c085:108::4) by mail.thefacebook.com (2620:10d:c085:11d::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Mon, 4 Oct 2021 22:28:33 -0700 Received: by devvm660.prn0.facebook.com (Postfix, from userid 385188) id D12D95346169; Mon, 4 Oct 2021 22:26:05 -0700 (PDT) From: To: CC: , , , , , , , , , , Peter Delevoryas Subject: [PATCH v3 0/2] hw/adc: Add basic Aspeed ADC model Date: Mon, 4 Oct 2021 22:26:02 -0700 Message-ID: <20211005052604.1674891-1-pdel@fb.com> X-Mailer: git-send-email 2.30.2 X-FB-Internal: Safe X-FB-Source: Intern X-Proofpoint-GUID: Nznu1zv_UBVpFKp1vooKQvkXG-omGqym X-Proofpoint-ORIG-GUID: Nznu1zv_UBVpFKp1vooKQvkXG-omGqym X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-04_05,2021-10-04_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=fb_default_notspam policy=fb_default score=0 clxscore=1015 phishscore=0 adultscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 malwarescore=0 suspectscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110050030 X-FB-Internal: deliver Received-SPF: pass client-ip=67.231.153.30; envelope-from=prvs=99121193c4=pdel@fb.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.066, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Peter Delevoryas v1: https://lore.kernel.org/qemu-devel/20211002214414.2858382-1-pdel@fbc.om/ v2: https://lore.kernel.org/qemu-devel/20211003191850.513658-1-pdel@fb.com/ v3: - Reduced the minimum access size to 2, to allow 16-bit reads - Shifted the read value down 16 bits when reading an odd channel's data register. So, v1 and v2 only attempted to support 32-bit reads and writes, but Patrick was testing Witherspoon with my patches and revealed that the upstream kernel driver (I was looking at 5.10 and 5.14) definitely performs 16-bit reads of each channel, and that my patches crash when that happens. https://lore.kernel.org/openbmc/YVtJTrgm3b3W4PY9@heinlein/ static int aspeed_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct aspeed_adc_data *data = iio_priv(indio_dev); const struct aspeed_adc_model_data *model_data = of_device_get_match_data(data->dev); switch (mask) { case IIO_CHAN_INFO_RAW: if (!strcmp(model_data->model_name, "ast2600-adc")) { *val = readw(data->base + chan->address) + data->cv; ^^^^^ } else { *val = readw(data->base + chan->address); ^^^^^ } return IIO_VAL_INT; I actually tested an image that uses this driver, but I wasn't testing reads through the driver, I was just using the QEMU monitor, so it didn't crash. It's easy to at least relax the restrictions enough to allow the 16-bit reads, and it's also not that hard to return the correct channel from the channel data sampling. I didn't attempt to do anything special for correctness of other registers, because I think we just perform 32-bit reads and writes for them, and I didn't attempt to do the correct thing for 16-bit writes to the data registers since that's not done by the driver. (And I'm not sure the hardware supports that anyways?) Thanks, Peter Andrew Jeffery (2): hw/adc: Add basic Aspeed ADC model hw/arm: Integrate ADC model into Aspeed SoC hw/adc/aspeed_adc.c | 427 ++++++++++++++++++++++++++++++++++++ hw/adc/meson.build | 1 + hw/adc/trace-events | 3 + hw/arm/aspeed_ast2600.c | 11 + hw/arm/aspeed_soc.c | 11 + include/hw/adc/aspeed_adc.h | 55 +++++ include/hw/arm/aspeed_soc.h | 2 + 7 files changed, 510 insertions(+) create mode 100644 hw/adc/aspeed_adc.c create mode 100644 include/hw/adc/aspeed_adc.h Interdiff against v2: diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c index fcd93d6853..c5fcae29f6 100644 --- a/hw/adc/aspeed_adc.c +++ b/hw/adc/aspeed_adc.c @@ -148,6 +148,11 @@ static uint64_t aspeed_adc_engine_read(void *opaque, hwaddr addr, /* fallthrough */ case DATA_CHANNEL_1_AND_0 ... DATA_CHANNEL_7_AND_6: value = read_channel_sample(s, reg); + /* Allow 16-bit reads of the data registers */ + if (addr & 0x2) { + assert(size == 2); + value >>= 16; + } break; default: qemu_log_mask(LOG_UNIMP, "%s: engine[%u]: 0x%" HWADDR_PRIx "\n", @@ -234,7 +239,7 @@ static const MemoryRegionOps aspeed_adc_engine_ops = { .write = aspeed_adc_engine_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { - .min_access_size = 4, + .min_access_size = 2, .max_access_size = 4, .unaligned = false, },