From patchwork Fri Sep 3 17:00:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1524453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull-eu.20150623.gappssmtp.com header.i=@vrull-eu.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=JmZZgQJt; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H1PLr0ZqJz9sR4 for ; Sat, 4 Sep 2021 03:05:40 +1000 (AEST) Received: from localhost ([::1]:42702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mMCdF-0004uA-S4 for incoming@patchwork.ozlabs.org; Fri, 03 Sep 2021 13:05:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mMCYz-0007Ju-T6 for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: from mail-lf1-x131.google.com ([2a00:1450:4864:20::131]:40935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mMCYx-00052Y-Ld for qemu-devel@nongnu.org; Fri, 03 Sep 2021 13:01:13 -0400 Received: by mail-lf1-x131.google.com with SMTP id bq28so12976329lfb.7 for ; Fri, 03 Sep 2021 10:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VvgWOZqK8pNWtJT1QOLtHEj6PXlVf5p9ZZ9y5BHBbi0=; b=JmZZgQJtQOwFNUv1AeAXX7LzKkgDV/gaJD4MZwpibiilAcUrRdQii/VQRyahz6V7LD kpaw/rcJ2kiQ5EH1SgZbtBzEmn5Bx+g58+qRNUc4MaeG+UiTygGlOmNu6BmGPzYiKVds 5wA38cCpC/R/Sb5Iz5Ri43kB+ohMkO674GLt4uPhk8yDkJiGPyQZG8v/q8XCzWaqFr1C 27EfZzay9ydill3peWFYtemQu/R+Owv8MzyXSKYjlnwXZ4vzwydhHHEtzly0GsKmCSNF pqevaYQlETOAZ9wyXNTe5EAPDURHTEsxedYVEzx7o2z8V3mERlqS8imlpiLWA8WFhM7U K5Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VvgWOZqK8pNWtJT1QOLtHEj6PXlVf5p9ZZ9y5BHBbi0=; b=DTaoh2xzSzpdHA1s6qUHHwaXZS00YZR5yUYuBJvGoOMygIJ8Swandh0bwR9Zi2/7Yt E6OcI3zmgGQYEDdQL1Zwa4U5HvKvDPh/tyZ3c3TyWM0+OiNIm1mtxO0EKPJpBHtxuDXd 4gAUYyG7Hn3S+KX7sa3q49np1p225GekQz0/HEJC8XnUYkRghl279GVerPoJPp2yWOhe czU9iGOi+aaVolpnmsjtan3D0cSO9D9a0KR+MPoY9n5iLiWh15408TFcB5qYhvptxcAp JjGL3VVq2XgaB2XuiqhuAEU5/SOsO6bNrS4N6qobBt+RWtlEGDYtSWXt4SF0XlTeBbe9 FrYA== X-Gm-Message-State: AOAM533HolBOLhB6fRXHkeSdTFQnn1c+gw6yj5IXuge6lvTTeFHjarPi edvM1ze2qlyDL2o14TUw7aE64aJRGTffZbNw1Ng= X-Google-Smtp-Source: ABdhPJywAyDVsrWi6N0g4vBMpiAEG5iePX6c11tlJA/8qDHvKaRXCJ4/lrJEgbkmDH0stDs+wjsldg== X-Received: by 2002:a05:6512:23a0:: with SMTP id c32mr3474192lfv.55.1630688469044; Fri, 03 Sep 2021 10:01:09 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c3sm628401ljj.77.2021.09.03.10.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 10:01:08 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v9 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Date: Fri, 3 Sep 2021 19:00:51 +0200 Message-Id: <20210903170100.2529121-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> References: <20210903170100.2529121-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x131.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove shift-one instructions in a separate commit. target/riscv/insn32.decode | 8 --- target/riscv/insn_trans/trans_rvb.c.inc | 70 ------------------------- 2 files changed, 78 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b499691a9e..e0f6e315a2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -693,8 +693,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -704,8 +702,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -717,15 +713,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 0763d0f836..860fbc3775 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); } -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -418,38 +380,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, EXT_NONE, gen_packuw); } -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift(ctx, a, EXT_ZERO, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - ctx->w = true; - return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32();