From patchwork Fri Sep 3 13:14:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1524325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull-eu.20150623.gappssmtp.com header.i=@vrull-eu.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=Xl/Me96p; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4H1Jbg2sT7z9sPf for ; Fri, 3 Sep 2021 23:31:27 +1000 (AEST) Received: from localhost ([::1]:59288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mM9Hx-0007S0-2x for incoming@patchwork.ozlabs.org; Fri, 03 Sep 2021 09:31:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mM91f-0002QX-Tz for qemu-devel@nongnu.org; Fri, 03 Sep 2021 09:14:35 -0400 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]:39807) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mM91c-0003gN-Se for qemu-devel@nongnu.org; Fri, 03 Sep 2021 09:14:35 -0400 Received: by mail-lj1-x22d.google.com with SMTP id q21so9554822ljj.6 for ; Fri, 03 Sep 2021 06:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rmA6mk06PJ6n3WtKBlk/DHFJLC4efi4TCq+bnBQAj2Q=; b=Xl/Me96p4G/kKBHKqBeBYNOC61+FLClgM7L4WWknO8sgPH8drIkWf0DTVPlQ+t5MJB 25/1szZjvFgz+pAtrF4DvwyMJRhQVvyQBgN9zMXRbfj4igBGor9DaSpQaPrzbGnzKOm7 OLi3m5jKKxdzdpe8Mrfl/7nm41s7b/Ti4fV3ik2u92lecRfJlgOr++JFETmioMIsDtUQ U6dALKT6hGqP+NWJWyd1HOA7kneewyNtGTNyQVN4TED+s7Lt99O1T7JeVYcHMuHOCADl KaxSqYgwAhWWExFWhT6WndnTVGS+MsHPgyJUHLLBiWpX+hIzrB01VthYsRYGuEiqrJfF j2SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rmA6mk06PJ6n3WtKBlk/DHFJLC4efi4TCq+bnBQAj2Q=; b=SLukR4x4XK6SH9X1lzGpVkVOjMPV1hWnzQPvTiMbUFBTYFcbDoBNo/y2vJ+C/MBK/J lXVBo6d1ksjVhpb2gnZwmU+ywvNEe2rrhQ3sZraaKj8t2C/x6Eh9xjuezYBKl0VKycGf 2MDZVeyvrjNt7nl+Y4mHCtNQSg6xsVU4F4/ZwptgIRIZQEs5hA5mEskFa6u6ZS2CHj4t xTeFgZapLs4KYlsEa3Ey13hhiRJwzUBwShf0E3ARuzIXZh+Q9YmOf7KjL1vA62tJ3gqR 606A7Kp5inYWoCy4bdETP3xFl2g8xVrqEItg/7Piq3cZY/eDpREN5PNQhe4WfIqZvAMn wG0Q== X-Gm-Message-State: AOAM531g9xanLPzUcauJK+bfPDtfBAW1Wrd3CLrfA9hCpxYaMm3Z9und cXDxu2cFIgb5DZNP7vl6pd7Eh48GmvwTG2Xyq7o= X-Google-Smtp-Source: ABdhPJz5leaVUiuOjUH8UnNtt4xfUGfG/RZHSY7+kc42m6DXtKY26f3I80nLJk/qNVpqlEk8xTVNLw== X-Received: by 2002:a2e:a36c:: with SMTP id i12mr2873397ljn.427.1630674871195; Fri, 03 Sep 2021 06:14:31 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id n5sm577995ljj.97.2021.09.03.06.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 06:14:30 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v8 12/14] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Date: Fri, 3 Sep 2021 15:14:15 +0200 Message-Id: <20210903131417.2248471-13-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210903131417.2248471-1-philipp.tomsich@vrull.eu> References: <20210903131417.2248471-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v4) Changes in v4: - Renamed RV32 variant to zext_h_32. - Reordered trans_zext_h_{32,64} to be next to each other. Changes in v3: - Moved zext.h-addition & pack*-removal to a separate commit. target/riscv/insn32.decode | 12 ++++--- target/riscv/insn_trans/trans_rvb.c.inc | 46 ++++++++----------------- target/riscv/translate.c | 40 --------------------- 3 files changed, 21 insertions(+), 77 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 017eb50a49..abf794095a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -691,6 +691,9 @@ rori 01100 ............ 101 ..... 0010011 @sh sext_b 011000 000100 ..... 001 ..... 0010011 @r2 sext_h 011000 000101 ..... 001 ..... 0010011 @r2 xnor 0100000 .......... 100 ..... 0110011 @r +# The encoding for zext.h differs between RV32 and RV64. +# zext_h_32 denotes the RV32 variant. +zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2 # *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) *** clzw 0110000 00000 ..... 001 ..... 0011011 @r2 @@ -703,15 +706,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2 rolw 0110000 .......... 001 ..... 0111011 @r roriw 0110000 .......... 101 ..... 0011011 @sh5 rorw 0110000 .......... 101 ..... 0111011 @r +# The encoding for zext.h differs between RV32 and RV64. +# When executing on RV64, the encoding used in RV32 is an illegal +# instruction, so we use different handler functions to differentiate. +zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2 # *** RV32B Standard Extension *** -pack 0000100 .......... 100 ..... 0110011 @r -packu 0100100 .......... 100 ..... 0110011 @r -packh 0000100 .......... 111 ..... 0110011 @r # *** RV64B Standard Extension (in addition to RV32B) *** -packw 0000100 .......... 100 ..... 0111011 @r -packuw 0100100 .......... 100 ..... 0111011 @r # *** RV32 Zbc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 2f37bad477..ca389f4fe2 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -78,24 +78,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a) return gen_arith(ctx, a, tcg_gen_eqv_tl); } -static bool trans_pack(DisasContext *ctx, arg_pack *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_pack); -} - -static bool trans_packu(DisasContext *ctx, arg_packu *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packu); -} - -static bool trans_packh(DisasContext *ctx, arg_packh *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packh); -} - static bool trans_min(DisasContext *ctx, arg_min *a) { REQUIRE_ZBB(ctx); @@ -236,6 +218,20 @@ static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a) return gen_unary(ctx, a, &gen_orc_b); } +static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a) +{ + REQUIRE_32BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_ext16u_tl); +} + +static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, &tcg_gen_ext16u_tl); +} + #define GEN_TRANS_SHADD(SHAMT) \ static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \ @@ -269,20 +265,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a) return gen_unary(ctx, a, gen_cpopw); } -static bool trans_packw(DisasContext *ctx, arg_packw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packw); -} - -static bool trans_packuw(DisasContext *ctx, arg_packuw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_arith(ctx, a, gen_packuw); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f16ac8bb1a..639f34b8f6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -536,29 +536,6 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, return true; } -static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_deposit_tl(ret, arg1, arg2, - TARGET_LONG_BITS / 2, - TARGET_LONG_BITS / 2); -} - -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); - tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); - tcg_temp_free(t); -} - -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t = tcg_temp_new(); - tcg_gen_ext8u_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); - tcg_temp_free(t); -} - static void gen_sbop_mask(TCGv ret, TCGv shamt) { tcg_gen_movi_tl(ret, 1); @@ -635,23 +612,6 @@ static void gen_cpopw(TCGv ret, TCGv arg1) tcg_gen_ctpop_tl(ret, arg1); } -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t = tcg_temp_new(); - tcg_gen_ext16s_tl(t, arg2); - tcg_gen_deposit_tl(ret, arg1, t, 16, 48); - tcg_temp_free(t); -} - -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) -{ - TCGv t = tcg_temp_new(); - tcg_gen_shri_tl(t, arg1, 16); - tcg_gen_deposit_tl(ret, arg2, t, 0, 16); - tcg_gen_ext32s_tl(ret, ret); - tcg_temp_free(t); -} - static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) { TCGv_i32 t1 = tcg_temp_new_i32();