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envelope-from=prvs=8878769573=pdel@fb.com; helo=mx0b-00082601.pphosted.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.392, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Peter Delevoryas v1: https://lore.kernel.org/qemu-devel/20210831233140.2659116-1-pdel@fb.com/ v2: - Replaced AspeedMachineClass "serial_hd0" with "uart_default" - Removed "qdev_get_machine()" usage - Removed unnecessary aspeed.h (machine class) includes in device files - Added "uint32_t uart_default" to AspeedSoCState - Added "uart-default" uint32 property to AspeedSoCState - Set "uart-default" just before qdev_realize() NOTE: Still not totally sure I did this right, especially because I only initialized the properties in the aspeed_soc.c file (2400 + 2500), but not aspeed_ast2600.c (2600), but I guess that's because aspeed_soc_class_init is common to all the SoC's. Peter Delevoryas (1): hw/arm/aspeed: Allow machine to set UART default hw/arm/aspeed.c | 3 +++ hw/arm/aspeed_ast2600.c | 8 ++++---- hw/arm/aspeed_soc.c | 9 ++++++--- include/hw/arm/aspeed.h | 1 + include/hw/arm/aspeed_soc.h | 1 + 5 files changed, 15 insertions(+), 7 deletions(-) Interdiff against v1: Reviewed-by: Cédric Le Goater diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 74379907ff..a81e90c539 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -350,6 +350,8 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", ASPEED_SCU_PROT_KEY, &error_abort); } + qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", + amc->uart_default); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); memory_region_add_subregion(get_system_memory(), @@ -804,7 +806,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_parallel = 1; mc->default_ram_id = "ram"; amc->macs_mask = ASPEED_MAC0_ON; - amc->serial_hd0 = ASPEED_DEV_UART5; + amc->uart_default = ASPEED_DEV_UART5; aspeed_machine_class_props_init(oc); } diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 361a456214..b07fcf10a0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/misc/unimp.h" -#include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" #include "qemu/module.h" @@ -232,8 +231,6 @@ static uint64_t aspeed_calc_affinity(int cpu) static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) { int i; - AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine()); - AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); AspeedSoCState *s = ASPEED_SOC(dev); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); Error *err = NULL; @@ -325,9 +322,9 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } - /* Wire up the first serial device, usually either UART5 or UART1 */ - serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2, - aspeed_soc_get_irq(s, amc->serial_hd0), 38400, + /* UART - attach an 8250 to the IO space as our UART */ + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, + aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* I2C */ diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 77422bbeb1..09c0f83710 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/misc/unimp.h" -#include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" #include "qemu/module.h" @@ -222,8 +221,6 @@ static void aspeed_soc_init(Object *obj) static void aspeed_soc_realize(DeviceState *dev, Error **errp) { int i; - AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine()); - AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc); AspeedSoCState *s = ASPEED_SOC(dev); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); Error *err = NULL; @@ -290,9 +287,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); } - /* Wire up the first serial device, usually either UART5 or UART1 */ - serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2, - aspeed_soc_get_irq(s, amc->serial_hd0), 38400, + /* UART - attach an 8250 to the IO space as our UART */ + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, + aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* I2C */ @@ -442,6 +439,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) static Property aspeed_soc_properties[] = { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, + ASPEED_DEV_UART5), DEFINE_PROP_END_OF_LIST(), }; @@ -452,6 +451,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) dc->realize = aspeed_soc_realize; /* Reason: Uses serial_hds and nd_table in realize() directly */ dc->user_creatable = false; + device_class_set_props(dc, aspeed_soc_properties); } diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h index bc0f27885a..cbeacb214c 100644 --- a/include/hw/arm/aspeed.h +++ b/include/hw/arm/aspeed.h @@ -38,7 +38,7 @@ struct AspeedMachineClass { uint32_t num_cs; uint32_t macs_mask; void (*i2c_init)(AspeedMachineState *bmc); - uint32_t serial_hd0; + uint32_t uart_default; }; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index d9161d26d6..87d76c9259 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -65,6 +65,7 @@ struct AspeedSoCState { AspeedSDHCIState sdhci; AspeedSDHCIState emmc; AspeedLPCState lpc; + uint32_t uart_default; }; #define TYPE_ASPEED_SOC "aspeed-soc"