From patchwork Wed Aug 25 16:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1520887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull-eu.20150623.gappssmtp.com header.i=@vrull-eu.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=SgTn/B5l; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GvsyJ3T6Zz9sSs for ; Thu, 26 Aug 2021 03:13:44 +1000 (AEST) Received: from localhost ([::1]:46684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mIwT8-00063E-9W for incoming@patchwork.ozlabs.org; Wed, 25 Aug 2021 13:13:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mIwFg-0004Ye-RP for qemu-devel@nongnu.org; Wed, 25 Aug 2021 12:59:48 -0400 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]:45713) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mIwFe-0000c3-Ja for qemu-devel@nongnu.org; Wed, 25 Aug 2021 12:59:48 -0400 Received: by mail-lf1-x130.google.com with SMTP id g13so279694lfj.12 for ; Wed, 25 Aug 2021 09:59:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Ccr676R0L0N8dXIKtyLYzw3pvB6Fou3Jl1fzwXAYNY=; b=SgTn/B5lFRUOFppUd2LJeNAOQG/aGHCgHqEos9AaPf0YYRdWpnKhXmHV+LOztYquUT xJigpfV03GUABkf9VWezScspx7dok7l9k/MtQ5kjxyH1C7SJHM+mpKgiY+e9KiKqlDNX w5gyM26cJbcVBmy+TWrHZBQ7Wa1QAZUf/xDJDq8zlbkkzA6TP4GXbpe/NETaJwRm72RJ 6l+m4/I4vsacehzMiCn95Auj/w89d3Innakat3rN/wYIygkwNgueDsMkH8jmUhKccYFb /o1Q/2ApV7Aa57wD3sZQ7HvlueuHxM4/wLj/i1oa8RWEHXRkB8bPZCbLklZ+EkZI8fwq igAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Ccr676R0L0N8dXIKtyLYzw3pvB6Fou3Jl1fzwXAYNY=; b=FmLT4aT17+KN7FT8PDBQQ9tTkizIYxAMO+NF/KWNhz/WUDaWv1Sp5eULdSdpTYR1Zw OhhU6eJKLKD3lkZaugvkoPtyri/26cQ2rBg50tfHHgso/oZj7jPHIoUgxJ2dvHxVM/zC qMMrEYM50dH+ndFIrcx13n6w9f9SyEJ3xKCNUnD9WMI+IGH/fdNinPcxVrz96qXRxND9 mTNXRCBluhjTDgVQV97WOLqxvBBDJnG9Oo2rCgVkFM+UldGgz2+ZWIuV+lgv8z7n4fLl GW3LH83+4NBuprRmxgIg6I4I/k383B+edUyV4HWkSLw/rzAf5rri6ltCPzzhGWow6meH WbbQ== X-Gm-Message-State: AOAM5325NiBmWHgZM0i3dkdHsaqb2aljK6YVQJskP2CEiKnVKFMvJqc+ 03HtlXHQaiqMzBOoFYEbMC4TgpDK4yGsVkgK X-Google-Smtp-Source: ABdhPJz+mr5RZo2WCpCW3sD/wsqYdgRigK6v7vsBBY6EXVRUahdXnFD3yaLZh65trLtPrFhYnTMV6w== X-Received: by 2002:a19:ae03:: with SMTP id f3mr16830674lfc.192.1629910784859; Wed, 25 Aug 2021 09:59:44 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id r2sm59619ljj.14.2021.08.25.09.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 09:59:44 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v6 05/14] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Date: Wed, 25 Aug 2021 18:58:58 +0200 Message-Id: <20210825165907.34026-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210825165907.34026-1-philipp.tomsich@vrull.eu> References: <20210825165907.34026-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x130.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Kito Cheng , Richard Henderson , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The Zb[abcs] ratification package does not include the proposed shift-one instructions. There currently is no clear plan to whether these (or variants of them) will be ratified as Zbo (or a different extension) or what the timeframe for such a decision could be. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- (no changes since v3) Changes in v3: - Remove shift-one instructions in a separate commit. target/riscv/insn32.decode | 8 ---- target/riscv/insn_trans/trans_rvb.c.inc | 52 ------------------------- target/riscv/translate.c | 14 ------- 3 files changed, 74 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9abdbcb799..7e38477553 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -692,8 +692,6 @@ bset 0010100 .......... 001 ..... 0110011 @r bclr 0100100 .......... 001 ..... 0110011 @r binv 0110100 .......... 001 ..... 0110011 @r bext 0100100 .......... 101 ..... 0110011 @r -slo 0010000 .......... 001 ..... 0110011 @r -sro 0010000 .......... 101 ..... 0110011 @r ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r @@ -703,8 +701,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh bclri 01001. ........... 001 ..... 0010011 @sh binvi 01101. ........... 001 ..... 0010011 @sh bexti 01001. ........... 101 ..... 0010011 @sh -sloi 00100. ........... 001 ..... 0010011 @sh -sroi 00100. ........... 101 ..... 0010011 @sh rori 01100. ........... 101 ..... 0010011 @sh grevi 01101. ........... 101 ..... 0010011 @sh gorci 00101. ........... 101 ..... 0010011 @sh @@ -716,15 +712,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 packw 0000100 .......... 100 ..... 0111011 @r packuw 0100100 .......... 100 ..... 0111011 @r -slow 0010000 .......... 001 ..... 0111011 @r -srow 0010000 .......... 101 ..... 0111011 @r rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r -sloiw 0010000 .......... 001 ..... 0011011 @sh5 -sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 975492d45c..ac706349f5 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -162,30 +162,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } -static bool trans_slo(DisasContext *ctx, arg_slo *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_slo); -} - -static bool trans_sloi(DisasContext *ctx, arg_sloi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_slo); -} - -static bool trans_sro(DisasContext *ctx, arg_sro *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shift(ctx, a, gen_sro); -} - -static bool trans_sroi(DisasContext *ctx, arg_sroi *a) -{ - REQUIRE_EXT(ctx, RVB); - return gen_shifti(ctx, a, gen_sro); -} - static bool trans_ror(DisasContext *ctx, arg_ror *a) { REQUIRE_EXT(ctx, RVB); @@ -279,34 +255,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a) return gen_arith(ctx, a, gen_packuw); } -static bool trans_slow(DisasContext *ctx, arg_slow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_slo); -} - -static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_slo); -} - -static bool trans_srow(DisasContext *ctx, arg_srow *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftw(ctx, a, gen_sro); -} - -static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) -{ - REQUIRE_64BIT(ctx); - REQUIRE_EXT(ctx, RVB); - return gen_shiftiw(ctx, a, gen_sro); -} - static bool trans_rorw(DisasContext *ctx, arg_rorw *a) { REQUIRE_64BIT(ctx); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6983be5723..fc22ae82d0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -595,20 +595,6 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) tcg_gen_andi_tl(ret, ret, 1); } -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shl_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) -{ - tcg_gen_not_tl(ret, arg1); - tcg_gen_shr_tl(ret, ret, arg2); - tcg_gen_not_tl(ret, ret); -} - static bool gen_grevi(DisasContext *ctx, arg_grevi *a) { TCGv source1 = tcg_temp_new();