From patchwork Mon Aug 23 16:40:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 1519852 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=vrull-eu.20150623.gappssmtp.com header.i=@vrull-eu.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=T83w1rbt; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GtdVt1nSVz9sWX for ; Tue, 24 Aug 2021 02:49:10 +1000 (AEST) Received: from localhost ([::1]:44674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mID8G-0004fQ-0i for incoming@patchwork.ozlabs.org; Mon, 23 Aug 2021 12:49:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mID0F-0006EU-9I for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:51 -0400 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]:33519) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mID0A-0006HK-IM for qemu-devel@nongnu.org; Mon, 23 Aug 2021 12:40:50 -0400 Received: by mail-lj1-x233.google.com with SMTP id s12so7407226ljg.0 for ; Mon, 23 Aug 2021 09:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull-eu.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VEoCDINFgPbEp42QED+f3EBPY61v48BREXQWFSwsRt8=; b=T83w1rbtuCWQ61X22N5E55bPRwwwGLaY0XXUQ4G047NW4UtluEA0ZmLbAPq6d8Ug6o h3DZAHfWxPQ5vqzwXmp871wGKCLckBJLXtbeOY+JF7Lxi4o6/I5R3nQXQu2fZ/zPZ1eK hrpogdYOOLbo5T3b414pSCb4BMZ0QrAxdZ4sJxVz/7o4b9Ay6W1Lt7BxvqVXB6x1fRPS 6uekTUN1cd/R0ZAcGmpTApDvWBJfO5OB0Y2zxNWBEaI7MPkE9iLmvWgj63MUP+F4Y7yz St2J/hbz4fOR1v2Ne/yI3v0oQIfhSvl5wPs72oC4FRjyExu/wd1nb/NRUd7n9fZVD55K 1T5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VEoCDINFgPbEp42QED+f3EBPY61v48BREXQWFSwsRt8=; b=HhjySgC8jYcvhtrj1RjwBD06eaAtqwY5ekgIc+wISvIXj08w3RzP48iqzWfLVKFHtZ Lx3P4LD57XwaAgFykkpiolFYqJD3Ewdp592m4Dd+4iQHQI6yid2e+Zy/KoqqVJS6xWxz +w9zH1NRVQMvk6EF+ziSpQVf6n939uNYBizthwCKJH2zn5+jwi9HmpPDwGJsTN5u8rMK VH9+Zm8h+xm3N+4abXEXOUy4tx1Pw6aCtneOMoQEjbh1nceH9W7qE7ZS/38U1tiMPZBf Ch8sCCaK4VzDU045gp4A36SR76Ba1K/TcpypeAplvobErEFwe1ygonYAfA82ViL2hbJg 6Z2g== X-Gm-Message-State: AOAM530KwaFVXTgLrKAlSQMt/t6HgOCLgszotp7aEPS5vHM7Gb05MIZO IXo+k78UrPfDtkkEdT6eTLh9ZOXtqvxmVS8C X-Google-Smtp-Source: ABdhPJxg5gy9q9aUpm0hBHaVNx0uKN+sq1EhpJTslmIwrkVC1t9jNXkuGcZVTNPmJNtNm/HoWS35Kg== X-Received: by 2002:a2e:9e53:: with SMTP id g19mr29095544ljk.58.1629736842692; Mon, 23 Aug 2021 09:40:42 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id z5sm1491671lfs.126.2021.08.23.09.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:40:42 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v3 01/15] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Date: Mon, 23 Aug 2021 18:40:24 +0200 Message-Id: <20210823164038.2195113-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> References: <20210823164038.2195113-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The bitmanipulation ISA extensions will be ratified as individual small extension packages instead of a large B-extension. The first new instructions through the door (these have completed public review) are Zb[abcs]. This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for these in target/riscv/cpu.[ch]. Signed-off-by: Philipp Tomsich Reviewed-by: Richard Henderson --- Changes in v3: - Split off removal of 'x-b' property and 'ext_b' field into a separate patch to ensure bisectability. target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 991a6bb760..c7bc1f9f44 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -585,6 +585,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), + DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), + DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), + DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), + DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bf1c899c00..7c4cd8ea89 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -293,6 +293,10 @@ struct RISCVCPU { bool ext_u; bool ext_h; bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; bool ext_counters; bool ext_ifencei; bool ext_icsr;