@@ -13,6 +13,7 @@
#include "libqos/libqtest.h"
#include "libqos/qgraph.h"
#include "libqos/pci.h"
+#include "include/block/nvme.h"
typedef struct QNvme QNvme;
@@ -66,12 +67,65 @@ static void nvmetest_oob_cmb_test(void *obj, void *data, QGuestAllocator *alloc)
g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211);
}
+static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)
+{
+ QNvme *nvme = obj;
+ QPCIDevice *pdev = &nvme->dev;
+ QPCIBar pmr_bar, nvme_bar;
+ uint32_t pmrcap, pmrsts;
+
+ qpci_device_enable(pdev);
+ pmr_bar = qpci_iomap(pdev, 4, NULL);
+
+ /* Without Enabling PMRCTL check bar enablemet */
+ qpci_io_writel(pdev, pmr_bar, 0, 0xccbbaa99);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x99);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0xaa99);
+
+ /* Map NVMe Bar Register to Enable the Mem Region */
+ nvme_bar = qpci_iomap(pdev, 0, NULL);
+
+ pmrcap = qpci_io_readl(pdev, nvme_bar, 0xe00);
+ g_assert_cmpint(NVME_PMRCAP_RDS(pmrcap), ==, 0x1);
+ g_assert_cmpint(NVME_PMRCAP_WDS(pmrcap), ==, 0x1);
+ g_assert_cmpint(NVME_PMRCAP_BIR(pmrcap), ==, 0x4);
+ g_assert_cmpint(NVME_PMRCAP_PMRWBM(pmrcap), ==, 0x2);
+ g_assert_cmpint(NVME_PMRCAP_CMSS(pmrcap), ==, 0x1);
+
+ /* Enable PMRCTRL */
+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x1);
+
+ qpci_io_writel(pdev, pmr_bar, 0, 0x44332211);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), ==, 0x11);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), ==, 0x2211);
+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), ==, 0x44332211);
+
+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x0);
+
+ /* Disable PMRCTRL */
+ qpci_io_writel(pdev, nvme_bar, 0xe04, 0x0);
+
+ qpci_io_writel(pdev, pmr_bar, 0, 0x88776655);
+ g_assert_cmpint(qpci_io_readb(pdev, pmr_bar, 0), !=, 0x55);
+ g_assert_cmpint(qpci_io_readw(pdev, pmr_bar, 0), !=, 0x6655);
+ g_assert_cmpint(qpci_io_readl(pdev, pmr_bar, 0), !=, 0x88776655);
+
+ pmrsts = qpci_io_readl(pdev, nvme_bar, 0xe08);
+ g_assert_cmpint(NVME_PMRSTS_NRDY(pmrsts), ==, 0x1);
+
+ qpci_iounmap(pdev, nvme_bar);
+ qpci_iounmap(pdev, pmr_bar);
+}
+
static void nvme_register_nodes(void)
{
QOSGraphEdgeOptions opts = {
.extra_device_opts = "addr=04.0,drive=drv0,serial=foo",
.before_cmd_line = "-drive id=drv0,if=none,file=null-co://,"
- "file.read-zeroes=on,format=raw",
+ "file.read-zeroes=on,format=raw "
+ "-object memory-backend-ram,id=pmr0,"
+ "share=on,size=8",
};
add_qpci_address(&opts, &(QPCIAddress) { .devfn = QPCI_DEVFN(4, 0) });
@@ -83,6 +137,11 @@ static void nvme_register_nodes(void)
qos_add_test("oob-cmb-access", "nvme", nvmetest_oob_cmb_test, &(QOSGraphTestOptions) {
.edge.extra_device_opts = "cmb_size_mb=2"
});
+
+ qos_add_test("pmr-test-access", "nvme", nvmetest_pmr_reg_test,
+ &(QOSGraphTestOptions) {
+ .edge.extra_device_opts = "pmrdev=pmr0"
+ });
}
libqos_init(nvme_register_nodes);