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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4sm12650096pji.52.2021.07.05.20.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jul 2021 20:50:18 -0700 (PDT) From: Kito Cheng To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org Subject: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Date: Tue, 6 Jul 2021 11:50:15 +0800 Message-Id: <20210706035015.122899-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=kito.cheng@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Set I, M, A, F, D and C bit for hwcap if misa is set. V3 Changes: - Simplify logic of getting hwcap. V2 Changes: - Only set imafdc bits, sync with upstream linux kernel. Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson --- linux-user/elfload.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 598ab8aa13..42ef2a1148 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #define ELF_CLASS ELFCLASS64 #endif +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ +#define MISA_BIT(EXT) (1 << (EXT - 'A')) + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + + return cpu->env.misa & mask; +#undef MISA_BIT +} + static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) {