| Message ID | 20210409074857.166082-6-zhiwei_liu@c-sky.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: support clic v0.9 specification | expand |
LIU Zhiwei <zhiwei_liu@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道： > The xip CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- > target/riscv/csr.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 74bc7a08aa..f6c84b9fe4 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -735,6 +735,11 @@ static int rmw_mip(CPURISCVState *env, int csrno, > target_ulong *ret_value, > target_ulong mask = write_mask & delegable_ints & ~env->miclaim; > uint32_t old_mip; > > + /* The xip CSR appears hardwired to zero in CLIC mode. (Section 4.3) > */ > + if (riscv_clic_is_clic_mode(env)) { > + *ret_value = 0; > + return 0; > Should return RISCV_EXCP_NONE when you rebase to the latest master branch. Same to rmw_sip(). Reviewed-by: Frank Chang <frank.chang@sifive.com> > + } > if (mask) { > old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); > } else { > @@ -922,6 +927,11 @@ static int rmw_sip(CPURISCVState *env, int csrno, > target_ulong *ret_value, > if (riscv_cpu_virt_enabled(env)) { > ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); > } else { > + /* The xip CSR appears hardwired to zero in CLIC mode. (Section > 4.3) */ > + if (riscv_clic_is_clic_mode(env)) { > + *ret_value = 0; > + return 0; > + } > ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, > write_mask & env->mideleg & sip_writable_mask); > } > -- > 2.25.1 > > >
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 74bc7a08aa..f6c84b9fe4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -735,6 +735,11 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong mask = write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; + /* The xip CSR appears hardwired to zero in CLIC mode. (Section 4.3) */ + if (riscv_clic_is_clic_mode(env)) { + *ret_value = 0; + return 0; + } if (mask) { old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask)); } else { @@ -922,6 +927,11 @@ static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value, if (riscv_cpu_virt_enabled(env)) { ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask); } else { + /* The xip CSR appears hardwired to zero in CLIC mode. (Section 4.3) */ + if (riscv_clic_is_clic_mode(env)) { + *ret_value = 0; + return 0; + } ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value, write_mask & env->mideleg & sip_writable_mask); }
The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> --- target/riscv/csr.c | 10 ++++++++++ 1 file changed, 10 insertions(+)