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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id u17sm16189542wmj.35.2021.01.23.18.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Jan 2021 18:53:11 -0800 (PST) From: Leif Lindholm To: qemu-arm@nongnu.org Subject: [RFC PATCH 4/4] hw/intc: make gicv3_idreg() distinguish between gicv3/gicv4 Date: Sun, 24 Jan 2021 02:53:06 +0000 Message-Id: <20210124025306.3949-5-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210124025306.3949-1-leif@nuviainc.com> References: <20210124025306.3949-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Shashi Mallela , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make gicv3_idreg() able to return either gicv3 or gicv4 data. Add a parameter to specify gic version. Signed-off-by: Leif Lindholm --- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 2 +- hw/intc/gicv3_internal.h | 12 ++++++++++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 833deb0a74..d32a1d5f48 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -544,7 +544,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, } case GICD_IDREGS ... GICD_IDREGS + 0x2f: /* ID registers */ - *data = gicv3_idreg(offset - GICD_IDREGS); + *data = gicv3_idreg(offset - GICD_IDREGS, s->revision); return MEMTX_OK; case GICD_SGIR: /* WO registers, return unknown value */ diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 544f4d82ff..faa68c9a71 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -239,7 +239,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, *data = cs->gicr_nsacr; return MEMTX_OK; case GICR_IDREGS ... GICR_IDREGS + 0x2f: - *data = gicv3_idreg(offset - GICR_IDREGS); + *data = gicv3_idreg(offset - GICR_IDREGS, cs->gic->revision); return MEMTX_OK; default: return MEMTX_ERROR; diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 05303a55c8..ded2df66eb 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -321,7 +321,7 @@ static inline uint32_t gicv3_iidr(void) return 0x43b; } -static inline uint32_t gicv3_idreg(int regoffset) +static inline uint32_t gicv3_idreg(int regoffset, int revision) { /* Return the value of the CoreSight ID register at the specified * offset from the first ID register (as found in the distributor @@ -331,7 +331,15 @@ static inline uint32_t gicv3_idreg(int regoffset) static const uint8_t gicd_ids[] = { 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 }; - return gicd_ids[regoffset / 4]; + static const uint8_t gicdv4_ids[] = { + 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x4B, 0x00, 0x0D, 0xF0, 0x05, 0xB1 + }; + + if (revision == 3) { + return gicd_ids[regoffset / 4]; + } else { + return gicdv4_ids[regoffset / 4]; + } } /**