From patchwork Fri Jan 22 12:07:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minwoo Im X-Patchwork-Id: 1430327 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=DHMKwkbq; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DMdN20qN3z9s2g for ; Fri, 22 Jan 2021 23:09:06 +1100 (AEDT) Received: from localhost ([::1]:46904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l2vFQ-0008TE-1p for incoming@patchwork.ozlabs.org; Fri, 22 Jan 2021 07:09:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l2vEV-0008P4-CC; Fri, 22 Jan 2021 07:08:07 -0500 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:46094) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l2vEK-0001t5-0T; Fri, 22 Jan 2021 07:08:05 -0500 Received: by mail-pg1-x52f.google.com with SMTP id c22so3525699pgg.13; Fri, 22 Jan 2021 04:07:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sJy8j7so+eEZG2Um9lFCjm7LQCU9N8yZbI2MukMkgVs=; b=DHMKwkbqJuopmA6kdf3W6R3uyo+gGVr6IuMIjmBFGK1odRGBapAlBf91ieau4XVgVD 8PLb0LPU0OjKvs2i++NTEEtcZd/BPyhVkcyj7TrQcr+dq4a5v4zblLkksf78cn0zCtDp 0evhJCxJwkTwz3iMwwHJqtCcS7R3JYRG08tM7JY2Rb1UDEye1sPNIybaBljTukHP8gxo jEYzGiEpIB+BxwkPshfAEWxjSB5Yj50zQoja+yE+UJvdKLOqKXFlyT7aLGM+EPq5FwEU +V+fO3cxcb3r+t4vbJvSl1YatblMTr9AvMooJY0qIR9NFuhfroRpnmC0WWwwFOrKAAy/ FOcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sJy8j7so+eEZG2Um9lFCjm7LQCU9N8yZbI2MukMkgVs=; b=irV20xgMO7TjOWCgoNRbNEtA/QIzc2Zp+uT7rdHS7xDIGasqfR3h6AC2LU2BMP5yW0 3rpTQhuD/ImBtqjqASfHpxRBr7z7jbDj8GgM7PiMQ4VSt3pcFxHoPFF73gTwYDE3rFFt Rnhqtckqb8ANFIWcNnpwcG55VDERLYxxT6sPWj/HMv02SdFsnRoIRrAlkOrIXncP16sU bJDRwK9aw6ctUlI8wRJDxlRq435Noqz2ye19kUaYGGGgf1mfbJMgSZiJ4/basWiPUedd xHWabKHiVBvGCPIuE8HSWxjm2DniZjo7qxa0/mazBr6k3y9eCszaODpzZbrsGWgx1kJO H43w== X-Gm-Message-State: AOAM531kPx0OUO6n6sXXYsPCX0PjhEmUeZgTT7w/QrQGcgz2sf27Gm0L l8CdBG7S3rjHwrZs9cCAaU1q98m5+IdSSw== X-Google-Smtp-Source: ABdhPJyi40H9B6EQFywoUGbj6EYVlY292ibsO6wdzHPZCG6dlXKEPdioHvDewnzoSR/LsR/uUNMntg== X-Received: by 2002:a62:25c7:0:b029:156:72a3:b0c0 with SMTP id l190-20020a6225c70000b029015672a3b0c0mr4413943pfl.59.1611317273754; Fri, 22 Jan 2021 04:07:53 -0800 (PST) Received: from localhost.localdomain ([211.108.35.36]) by smtp.gmail.com with ESMTPSA id mv17sm9104440pjb.17.2021.01.22.04.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jan 2021 04:07:53 -0800 (PST) From: Minwoo Im To: qemu-devel@nongnu.org, qemu-block@nongnu.org Subject: [PATCH V5 1/6] hw/block/nvme: introduce nvme-subsys device Date: Fri, 22 Jan 2021 21:07:31 +0900 Message-Id: <20210122120736.5242-2-minwoo.im.dev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210122120736.5242-1-minwoo.im.dev@gmail.com> References: <20210122120736.5242-1-minwoo.im.dev@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=minwoo.im.dev@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , Klaus Jensen , Minwoo Im , Kevin Wolf , Max Reitz Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To support multi-path in QEMU NVMe device model, We need to have NVMe subsystem hierarchy to map controllers and namespaces to a NVMe subsystem. This patch introduced a simple nvme-subsys device model. The subsystem will be prepared with subsystem NQN with provided in nvme-subsys device: ex) -device nvme-subsys,id=subsys0: nqn.2019-08.org.qemu:subsys0 Signed-off-by: Minwoo Im --- hw/block/meson.build | 2 +- hw/block/nvme-subsys.c | 60 ++++++++++++++++++++++++++++++++++++++++++ hw/block/nvme-subsys.h | 25 ++++++++++++++++++ hw/block/nvme.c | 3 +++ 4 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 hw/block/nvme-subsys.c create mode 100644 hw/block/nvme-subsys.h diff --git a/hw/block/meson.build b/hw/block/meson.build index 602ca6c8541d..83ea2d37978d 100644 --- a/hw/block/meson.build +++ b/hw/block/meson.build @@ -13,7 +13,7 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c')) softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('tc58128.c')) -softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c')) +softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.c', 'nvme-subsys.c')) specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c')) specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-blk.c')) diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c new file mode 100644 index 000000000000..aa82911b951c --- /dev/null +++ b/hw/block/nvme-subsys.c @@ -0,0 +1,60 @@ +/* + * QEMU NVM Express Subsystem: nvme-subsys + * + * Copyright (c) 2021 Minwoo Im + * + * This code is licensed under the GNU GPL v2. Refer COPYING. + */ + +#include "qemu/units.h" +#include "qemu/osdep.h" +#include "qemu/uuid.h" +#include "qemu/iov.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-core.h" +#include "hw/block/block.h" +#include "block/aio.h" +#include "block/accounting.h" +#include "sysemu/sysemu.h" +#include "hw/pci/pci.h" +#include "nvme.h" +#include "nvme-subsys.h" + +static void nvme_subsys_setup(NvmeSubsystem *subsys) +{ + snprintf((char *)subsys->subnqn, sizeof(subsys->subnqn), + "nqn.2019-08.org.qemu:%s", subsys->parent_obj.id); +} + +static void nvme_subsys_realize(DeviceState *dev, Error **errp) +{ + NvmeSubsystem *subsys = NVME_SUBSYS(dev); + + nvme_subsys_setup(subsys); +} + +static void nvme_subsys_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); + + dc->realize = nvme_subsys_realize; + dc->desc = "Virtual NVMe subsystem"; +} + +static const TypeInfo nvme_subsys_info = { + .name = TYPE_NVME_SUBSYS, + .parent = TYPE_DEVICE, + .class_init = nvme_subsys_class_init, + .instance_size = sizeof(NvmeSubsystem), +}; + +static void nvme_subsys_register_types(void) +{ + type_register_static(&nvme_subsys_info); +} + +type_init(nvme_subsys_register_types) diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h new file mode 100644 index 000000000000..40f06a4c7db0 --- /dev/null +++ b/hw/block/nvme-subsys.h @@ -0,0 +1,25 @@ +/* + * QEMU NVM Express Subsystem: nvme-subsys + * + * Copyright (c) 2021 Minwoo Im + * + * This code is licensed under the GNU GPL v2. Refer COPYING. + */ + +#ifndef NVME_SUBSYS_H +#define NVME_SUBSYS_H + +#define TYPE_NVME_SUBSYS "nvme-subsys" +#define NVME_SUBSYS(obj) \ + OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS) + +#define NVME_SUBSYS_MAX_CTRLS 32 + +typedef struct NvmeCtrl NvmeCtrl; +typedef struct NvmeNamespace NvmeNamespace; +typedef struct NvmeSubsystem { + DeviceState parent_obj; + uint8_t subnqn[256]; +} NvmeSubsystem; + +#endif /* NVME_SUBSYS_H */ diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 21aec90637fa..aabccdf36f4b 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -25,6 +25,7 @@ * mdts=,zoned.append_size_limit= \ * -device nvme-ns,drive=,bus=,nsid=,\ * zoned= + * -device nvme-subsys,id= * * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. By default, the @@ -38,6 +39,8 @@ * * The PMR will use BAR 4/5 exclusively. * + * To place controller(s) and namespace(s) to a subsystem, then provide + * nvme-subsys device as above. * * nvme device parameters * ~~~~~~~~~~~~~~~~~~~~~~