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Tue, 19 Jan 2021 05:15:10 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH v3 03/12] hw/block/nvme: indicate CMB support through controller capabilities register Date: Tue, 19 Jan 2021 11:14:55 +0100 Message-Id: <20210119101504.231259-4-its@irrelevant.dk> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210119101504.231259-1-its@irrelevant.dk> References: <20210119101504.231259-1-its@irrelevant.dk> MIME-Version: 1.0 Received-SPF: pass client-ip=64.147.123.17; envelope-from=its@irrelevant.dk; helo=wnew3-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Andrzej Jakowski , Maxim Levitsky , Stefan Hajnoczi , Klaus Jensen , Minwoo Im Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Andrzej Jakowski This patch sets CMBS bit in controller capabilities register when user configures NVMe driver with CMB support, so capabilites are correctly reported to guest OS. Signed-off-by: Andrzej Jakowski Reviewed-by: Maxim Levitsky Reviewed-by: Minwoo Im Signed-off-by: Klaus Jensen --- include/block/nvme.h | 10 +++++++--- hw/block/nvme.c | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index 45b2678db1f0..86d7fc2f905c 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -36,6 +36,7 @@ enum NvmeCapShift { CAP_MPSMIN_SHIFT = 48, CAP_MPSMAX_SHIFT = 52, CAP_PMR_SHIFT = 56, + CAP_CMB_SHIFT = 57, }; enum NvmeCapMask { @@ -49,6 +50,7 @@ enum NvmeCapMask { CAP_MPSMIN_MASK = 0xf, CAP_MPSMAX_MASK = 0xf, CAP_PMR_MASK = 0x1, + CAP_CMB_MASK = 0x1, }; #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -78,9 +80,11 @@ enum NvmeCapMask { #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\ << CAP_MPSMIN_SHIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ - << CAP_MPSMAX_SHIFT) -#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\ - << CAP_PMR_SHIFT) + << CAP_MPSMAX_SHIFT) +#define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK) \ + << CAP_PMR_SHIFT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK) \ + << CAP_CMB_SHIFT) enum NvmeCapCss { NVME_CAP_CSS_NVM = 1 << 0, diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9a508df8d200..3168ba5114ed 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -4345,6 +4345,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_CSI_SUPP); NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY); NVME_CAP_SET_MPSMAX(n->bar.cap, 4); + NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0); n->bar.vs = NVME_SPEC_VER; n->bar.intmc = n->bar.intms = 0;