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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id b19sm12353373wmj.37.2021.01.08.10.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jan 2021 10:51:56 -0800 (PST) From: Leif Lindholm To: qemu-devel@nongnu.org Subject: [PATCH v3 2/6] target/arm: make ARMCPU.clidr 64-bit Date: Fri, 8 Jan 2021 18:51:50 +0000 Message-Id: <20210108185154.8108-3-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210108185154.8108-1-leif@nuviainc.com> References: <20210108185154.8108-1-leif@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=leif@nuviainc.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Laurent Desnogues --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5e3cf77ec7..fadd1a47df 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.