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Wed, 23 Dec 2020 22:18:20 -0500 (EST) From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v3 3/8] hw/pci-host/bonito: Fixup IRQ mapping Date: Thu, 24 Dec 2020 11:17:45 +0800 Message-Id: <20201224031750.52146-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201224031750.52146-1-jiaxun.yang@flygoat.com> References: <20201224031750.52146-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Received-SPF: permerror client-ip=66.111.4.229; envelope-from=jiaxun.yang@flygoat.com; helo=new3-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Accroading to arch/mips/pci/fixup-fuloong2e.c in kernel, despites south bridge IRQs needs special care, all other IRQ pins are mapped by 'LOONGSON_IRQ_BASE + 25 + pin'. As south bridge IRQs are all handled by ISA bus, we can make a simple direct mapping. Signed-off-by: Jiaxun Yang --- v3: Define BONITO_PCI_IRQ_BASE for readability (f4bug) --- hw/pci-host/bonito.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index a99eced065..3fad470fc6 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -62,6 +62,9 @@ #define DPRINTF(fmt, ...) #endif +/* PCI slots IRQ pins start position */ +#define BONITO_PCI_IRQ_BASE 25 + /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ #define BONITO_BOOT_BASE 0x1fc00000 #define BONITO_BOOT_SIZE 0x00100000 @@ -546,19 +549,16 @@ static const MemoryRegionOps bonito_spciconf_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -#define BONITO_IRQ_BASE 32 - static void pci_bonito_set_irq(void *opaque, int irq_num, int level) { BonitoState *s = opaque; qemu_irq *pic = s->pic; PCIBonitoState *bonito_state = s->pci_dev; - int internal_irq = irq_num - BONITO_IRQ_BASE; - if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { + if (bonito_state->regs[BONITO_INTEDGE] & (1 << irq_num)) { qemu_irq_pulse(*pic); } else { /* level triggered */ - if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { + if (bonito_state->regs[BONITO_INTPOL] & (1 << irq_num)) { qemu_irq_raise(*pic); } else { qemu_irq_lower(*pic); @@ -566,25 +566,9 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level) } } -/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ -static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_bonito_map_irq(PCIDevice *pci_dev, int pin) { - int slot; - - slot = (pci_dev->devfn >> 3); - - switch (slot) { - case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ - return irq_num % 4 + BONITO_IRQ_BASE; - case 6: /* FULOONG2E_ATI_SLOT, VGA */ - return 4 + BONITO_IRQ_BASE; - case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */ - return 5 + BONITO_IRQ_BASE; - case 8 ... 12: /* PCI slot 1 to 4 */ - return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; - default: /* Unknown device, don't do any translation */ - return irq_num; - } + return BONITO_PCI_IRQ_BASE + pin; } static void bonito_reset(void *opaque)