| Message ID | 20201208122306.8933-3-leif@nuviainc.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: various changes to cpu.h | expand |
On 12/8/20 1:23 PM, Leif Lindholm wrote: > The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit > 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. > Extend the clidr field to be able to hold this context. > > Signed-off-by: Leif Lindholm <leif@nuviainc.com> > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Tue, 8 Dec 2020 at 12:23, Leif Lindholm <leif@nuviainc.com> wrote: > > The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit > 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. > Extend the clidr field to be able to hold this context. > > Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> (checked that none of the uses of this field are implicitly assuming it's 32-bits.) thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6962ef05d6..b54d1dc092 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,7 +938,7 @@ struct ARMCPU { uint32_t id_afr0; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t clidr; + uint64_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit 32, as well as adding a Ttype<n> field when FEAT_MTE is implemented. Extend the clidr field to be able to hold this context. Signed-off-by: Leif Lindholm <leif@nuviainc.com> --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)