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[73.47.162.176]) by smtp.gmail.com with ESMTPSA id p20sm220766pjg.44.2020.08.19.11.30.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Aug 2020 11:30:19 -0700 (PDT) From: Robert Foley To: qemu-devel@nongnu.org Subject: [PATCH v2 2/7] target/arm: add ARMCPUClass->do_interrupt_locked Date: Wed, 19 Aug 2020 14:28:51 -0400 Message-Id: <20200819182856.4893-3-robert.foley@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200819182856.4893-1-robert.foley@linaro.org> References: <20200819182856.4893-1-robert.foley@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=robert.foley@linaro.org; helo=mail-pf1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , robert.foley@linaro.org, "open list:ARM TCG CPUs" , peter.puhov@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Adding ->do_interrupt_locked to ARMCPUClass is preparation for pushing the BQL down into the per-arch implementation of ->do_interrupt. This is needed since ARM's *_cpu_exec_interrupt calls to *_do_interrupt. With the push down of the BQL into *_cpu_exec_interrupt and *_do_interrupt, *_cpu_exec_interrupt will call to ->do_interrupt with lock held. Since ->do_interrupt also has the lock, we need a way to allow cpu_exec_interrupt to call do_interrupt with lock held. This patch solves this issue of *_cpu_exec_interrupt needing to call do_interrupt with lock held. This patch is part of a series of transitions to move the BQL down into the do_interrupt per arch functions. This set of transitions is needed to maintain bisectability. This approach was suggested by Paolo Bonzini. For reference, here are two key posts in the discussion, explaining the reasoning/benefits of this approach. https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00784.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg01517.html https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html Signed-off-by: Robert Foley Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.c | 5 +++-- target/arm/cpu_tcg.c | 5 +++-- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 56395b87f6..264280194c 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -48,6 +48,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); * ARMCPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @do_interrupt_locked: Handler for interrupts (lock already held). * * An ARM CPU model. */ @@ -59,6 +60,8 @@ typedef struct ARMCPUClass { const ARMCPUInfo *info; DeviceRealize parent_realize; DeviceReset parent_reset; + + void (*do_interrupt_locked)(CPUState *cpu); } ARMCPUClass; typedef struct ARMCPU ARMCPU; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 46c1d92080..d15b459399 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -526,7 +526,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); + ARMCPUClass *acc = ARM_CPU_GET_CLASS(cs); CPUARMState *env = cs->env_ptr; uint32_t cur_el = arm_current_el(env); bool secure = arm_is_secure(env); @@ -573,7 +573,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) found: cs->exception_index = excp_idx; env->exception.target_el = target_el; - cc->do_interrupt(cs); + acc->do_interrupt_locked(cs); return true; } @@ -2225,6 +2225,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_cpu_do_interrupt_locked; + acc->do_interrupt_locked = arm_cpu_do_interrupt_locked; cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs = arm_asidx_from_attrs; cc->vmsd = &vmstate_arm_cpu; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 2fc7a29340..caf0d54c2c 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -17,7 +17,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - CPUClass *cc = CPU_GET_CLASS(cs); + ARMCPUClass *acc = ARM_CPU_GET_CLASS(cs); ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; bool ret = false; @@ -33,7 +33,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) if (interrupt_request & CPU_INTERRUPT_HARD && (armv7m_nvic_can_take_pending_exception(env->nvic))) { cs->exception_index = EXCP_IRQ; - cc->do_interrupt(cs); + acc->do_interrupt_locked(cs); ret = true; } return ret; @@ -602,6 +602,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifndef CONFIG_USER_ONLY cc->do_interrupt = arm_v7m_cpu_do_interrupt_locked; + acc->do_interrupt_locked = arm_v7m_cpu_do_interrupt_locked; #endif cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;