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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id d9sm16478588pgv.45.2020.08.17.01.52.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2020 01:52:11 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension Date: Mon, 17 Aug 2020 16:49:30 +0800 Message-Id: <20200817084955.28793-46-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200817084955.28793-1-frank.chang@sifive.com> References: <20200817084955.28793-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/translate.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 085381fee00..8844975bf94 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -512,6 +512,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zvqmac", RISCVCPU, cfg.ext_vqmac, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 715faed8824..6e9b17c4e38 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,7 @@ typedef struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_vqmac; char *priv_spec; char *user_spec; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0b3f5f1b4ba..5817e9344e9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -75,6 +75,7 @@ typedef struct DisasContext { uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; + bool ext_vqmac; } DisasContext; #ifdef TARGET_RISCV64 @@ -870,6 +871,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; + ctx->ext_vqmac = cpu->cfg.ext_vqmac; ctx->vlen = cpu->cfg.vlen; ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);