| Message ID | 20200817084955.28793-46-frank.chang@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | support vector extension v1.0 | expand |
On 8/17/20 1:49 AM, frank.chang@sifive.com wrote: > From: Frank Chang <frank.chang@sifive.com> > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 1 + > target/riscv/translate.c | 2 ++ > 3 files changed, 4 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 8/29/20 1:17 PM, Richard Henderson wrote: > On 8/17/20 1:49 AM, frank.chang@sifive.com wrote: >> From: Frank Chang <frank.chang@sifive.com> >> >> Signed-off-by: Frank Chang <frank.chang@sifive.com> >> --- >> target/riscv/cpu.c | 1 + >> target/riscv/cpu.h | 1 + >> target/riscv/translate.c | 2 ++ >> 3 files changed, 4 insertions(+) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> On second thought, the current manual says # This is only a proposal for a future extension after v1.0 and might change substantially before ratifcation. and does not even include the opcodes for these. I think we should focus on 1.0 and drop this extension for now. r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 085381fee00..8844975bf94 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -512,6 +512,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zvqmac", RISCVCPU, cfg.ext_vqmac, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 715faed8824..6e9b17c4e38 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,6 +285,7 @@ typedef struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_vqmac; char *priv_spec; char *user_spec; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0b3f5f1b4ba..5817e9344e9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -75,6 +75,7 @@ typedef struct DisasContext { uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; + bool ext_vqmac; } DisasContext; #ifdef TARGET_RISCV64 @@ -870,6 +871,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; + ctx->ext_vqmac = cpu->cfg.ext_vqmac; ctx->vlen = cpu->cfg.vlen; ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);