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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:22:50 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 Date: Wed, 22 Jul 2020 17:16:38 +0800 Message-Id: <20200722091641.8834-76-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x531.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , =?utf-8?q?Alex_Benn=C3=A9e?= , Hsiangkai Wang , Richard Henderson , Laurent Vivier , Paolo Bonzini , Palmer Dabbelt , Bastian Koppelmann , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- configure | 2 +- gdb-xml/riscv-64bit-csr.xml | 7 ++++ gdb-xml/riscv-64bit-vector-128b.xml | 59 +++++++++++++++++++++++++++ gdb-xml/riscv-64bit-vector-256b.xml | 59 +++++++++++++++++++++++++++ gdb-xml/riscv-64bit-vector-512b.xml | 59 +++++++++++++++++++++++++++ target/riscv/gdbstub.c | 62 ++++++++++++++++++++++++++++- 6 files changed, 245 insertions(+), 3 deletions(-) create mode 100644 gdb-xml/riscv-64bit-vector-128b.xml create mode 100644 gdb-xml/riscv-64bit-vector-256b.xml create mode 100644 gdb-xml/riscv-64bit-vector-512b.xml diff --git a/configure b/configure index ee6c3c6792..8d69013a97 100755 --- a/configure +++ b/configure @@ -8228,7 +8228,7 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-fpu.xml riscv-64bit-vector-128b.xml riscv-64bit-vector-256b.xml riscv-64bit-vector-512b.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; rx) TARGET_ARCH=rx diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml index 9039456293..28a7c9a9f3 100644 --- a/gdb-xml/riscv-64bit-csr.xml +++ b/gdb-xml/riscv-64bit-csr.xml @@ -248,4 +248,11 @@ + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-128b.xml b/gdb-xml/riscv-64bit-vector-128b.xml new file mode 100644 index 0000000000..f6150968b3 --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-128b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-256b.xml b/gdb-xml/riscv-64bit-vector-256b.xml new file mode 100644 index 0000000000..6183846a35 --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-256b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-vector-512b.xml b/gdb-xml/riscv-64bit-vector-512b.xml new file mode 100644 index 0000000000..78bb147cdf --- /dev/null +++ b/gdb-xml/riscv-64bit-vector-512b.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index f7c5212e27..1681f883e4 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -268,6 +268,13 @@ static int csr_register_map[] = { CSR_MUCOUNTEREN, CSR_MSCOUNTEREN, CSR_MHCOUNTEREN, + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VCSR, + CSR_VL, + CSR_VTYPE, + CSR_VLENB, }; int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) @@ -351,6 +358,34 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt = 0; + for (i = 0; i < vlenb; i += 8) { + cnt += gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i = 0; i < vlenb; i += 8) { + env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); + } + return vlenb; + } + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < ARRAY_SIZE(csr_register_map)) { @@ -416,15 +451,38 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa & RVV) { + /* TODO: support vlen other than 128, 256, 512 bits. */ + const char *vector_xml_name = NULL; + switch (cpu->cfg.vlen) { + case 128: + vector_xml_name = "riscv-64bit-vector-128b.xml"; + break; + case 256: + vector_xml_name = "riscv-64bit-vector-256b.xml"; + break; + case 512: + vector_xml_name = "riscv-64bit-vector-512b.xml"; + break; + default: + vector_xml_name = NULL; + break; + } + if (vector_xml_name) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, + riscv_gdb_set_vector, + 32, vector_xml_name, 0); + } + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 241, "riscv-32bit-csr.xml", 0); + 248, "riscv-32bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 241, "riscv-64bit-csr.xml", 0); + 248, "riscv-64bit-csr.xml", 0); gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-64bit-virtual.xml", 0);