@@ -2774,22 +2774,22 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
- uint32_t data = 0; \
- gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ REQUIRE_RVV; \
+ VEXT_CHECK_ISA_ILL(s); \
\
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- data = FIELD_DP32(data, VDATA, VMA, s->vma); \
- tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs1), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fn); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fn); \
+ gen_set_label(over); \
+ return true; \
}
GEN_MM_TRANS(vmand_mm)
@@ -4731,6 +4731,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta = vext_vta(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4740,8 +4741,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
+ if (vta == 1) { \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, i, 0); \
+ } \
} \
}