new file mode 100644
@@ -0,0 +1,142 @@
+#if XCHAL_HAVE_DFP || XCHAL_HAVE_FP_DIV
+#define DFPU 1
+#else
+#define DFPU 0
+#endif
+
+#define FCR_RM_NEAREST 0
+#define FCR_RM_TRUNC 1
+#define FCR_RM_CEIL 2
+#define FCR_RM_FLOOR 3
+
+#define FSR__ 0x00000000
+#define FSR_I 0x00000080
+#define FSR_U 0x00000100
+#define FSR_O 0x00000200
+#define FSR_Z 0x00000400
+#define FSR_V 0x00000800
+
+#define FSR_UI (FSR_U | FSR_I)
+#define FSR_OI (FSR_O | FSR_I)
+
+#define F32_0 0x00000000
+#define F32_0_5 0x3f000000
+#define F32_1 0x3f800000
+#define F32_MAX 0x7f7fffff
+#define F32_PINF 0x7f800000
+#define F32_NINF 0xff800000
+
+#define F32_DNAN 0x7fc00000
+#define F32_SNAN(v) (0x7f800000 | (v))
+#define F32_QNAN(v) (0x7fc00000 | (v))
+
+#define F32_MINUS 0x80000000
+
+#define F64_0 0x0000000000000000
+#define F64_MIN_NORM 0x0010000000000000
+#define F64_1 0x3ff0000000000000
+#define F64_MAX_2 0x7fe0000000000000
+#define F64_MAX 0x7fefffffffffffff
+#define F64_PINF 0x7ff0000000000000
+#define F64_NINF 0xfff0000000000000
+
+#define F64_DNAN 0x7ff8000000000000
+#define F64_SNAN(v) (0x7ff0000000000000 | (v))
+#define F64_QNAN(v) (0x7ff8000000000000 | (v))
+
+#define F64_MINUS 0x8000000000000000
+
+.macro test_op1_rm op, fr0, fr1, v0, r, sr
+ movi a2, 0
+ wur a2, fsr
+ movfp \fr0, \v0
+ \op \fr1, \fr0
+ check_res \fr1, \r, \sr
+.endm
+
+.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
+ movi a2, 0
+ wur a2, fsr
+ movfp \fr0, \v0
+ movfp \fr1, \v1
+ \op \fr2, \fr0, \fr1
+ check_res \fr2, \r, \sr
+.endm
+
+.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr
+ movi a2, 0
+ wur a2, fsr
+ movfp \fr0, \v0
+ movfp \fr1, \v1
+ movfp \fr2, \v2
+ \op \fr0, \fr1, \fr2
+ check_res \fr3, \r, \sr
+.endm
+
+.macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
+ movi a2, \rm
+ wur a2, fcr
+ test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
+ movi a2, (\rm) | 0x7c
+ wur a2, fcr
+ test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
+.endm
+
+.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr
+ movi a2, \rm
+ wur a2, fcr
+ test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
+ movi a2, (\rm) | 0x7c
+ wur a2, fcr
+ test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r, \sr
+.endm
+
+.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r, sr
+ movi a2, \rm
+ wur a2, fcr
+ test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
+ movi a2, (\rm) | 0x7c
+ wur a2, fcr
+ test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r, \sr
+.endm
+
+.macro test_op1 op, fr0, fr1, v0, r0, r1, r2, r3, sr0, sr1, sr2, sr3
+ test_op1_ex \op, \fr0, \fr1, \v0, 0, \r0, \sr0
+ test_op1_ex \op, \fr0, \fr1, \v0, 1, \r1, \sr1
+ test_op1_ex \op, \fr0, \fr1, \v0, 2, \r2, \sr2
+ test_op1_ex \op, \fr0, \fr1, \v0, 3, \r3, \sr3
+.endm
+
+.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3, sr0, sr1, sr2, sr3
+ test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0, \sr0
+ test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1, \sr1
+ test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2, \sr2
+ test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3, \sr3
+.endm
+
+.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3, sr0, sr1, sr2, sr3
+ test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0, \sr0
+ test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1, \sr1
+ test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2, \sr2
+ test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3, \sr3
+.endm
+
+.macro test_op2_cpe op
+ set_vector kernel, 2f
+ movi a2, 0
+ wsr a2, cpenable
+1:
+ \op f2, f0, f1
+ test_fail
+2:
+ rsr a2, excvaddr
+ movi a3, 1b
+ assert eq, a2, a3
+ rsr a2, exccause
+ movi a3, 32
+ assert eq, a2, a3
+
+ set_vector kernel, 0
+ movi a2, 1
+ wsr a2, cpenable
+.endm
@@ -1,4 +1,5 @@
#include "macros.inc"
+#include "fpu.h"
test_suite fp0_arith
@@ -9,84 +10,18 @@ test_suite fp0_arith
wfr \fr, a2
.endm
-.macro check_res fr, r
+.macro check_res fr, r, sr
rfr a2, \fr
dump a2
movi a3, \r
assert eq, a2, a3
rur a2, fsr
- assert eqi, a2, 0
-.endm
-
-.macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r
- movi a2, 0
- wur a2, fsr
- movfp \fr0, \v0
- movfp \fr1, \v1
- \op \fr2, \fr0, \fr1
- check_res \fr2, \r
-.endm
-
-.macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r
- movi a2, 0
- wur a2, fsr
- movfp \fr0, \v0
- movfp \fr1, \v1
- movfp \fr2, \v2
- \op \fr0, \fr1, \fr2
- check_res \fr3, \r
-.endm
-
-.macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r
- movi a2, \rm
- wur a2, fcr
- test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
- movi a2, (\rm) | 0x7c
- wur a2, fcr
- test_op2_rm \op, \fr0, \fr1, \fr2, \v0, \v1, \r
-.endm
-
-.macro test_op3_ex op, fr0, fr1, fr2, fr3, v0, v1, v2, rm, r
- movi a2, \rm
- wur a2, fcr
- test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
- movi a2, (\rm) | 0x7c
- wur a2, fcr
- test_op3_rm \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, \r
-.endm
-
-.macro test_op2 op, fr0, fr1, fr2, v0, v1, r0, r1, r2, r3
- test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 0, \r0
- test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 1, \r1
- test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 2, \r2
- test_op2_ex \op, \fr0, \fr1, \fr2, \v0, \v1, 3, \r3
-.endm
-
-.macro test_op3 op, fr0, fr1, fr2, fr3, v0, v1, v2, r0, r1, r2, r3
- test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 0, \r0
- test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 1, \r1
- test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 2, \r2
- test_op3_ex \op, \fr0, \fr1, \fr2, \fr3, \v0, \v1, \v2, 3, \r3
-.endm
-
-.macro test_op2_cpe op
- set_vector kernel, 2f
- movi a2, 0
- wsr a2, cpenable
-1:
- \op f2, f0, f1
- test_fail
-2:
- rsr a2, excvaddr
- movi a3, 1b
+#if DFPU
+ movi a3, \sr
assert eq, a2, a3
- rsr a2, exccause
- movi a3, 32
- assert eq, a2, a3
-
- set_vector kernel, 0
- movi a2, 1
- wsr a2, cpenable
+#else
+ assert eqi, a2, 0
+#endif
.endm
test add_s
@@ -94,78 +29,127 @@ test add_s
wsr a2, cpenable
test_op2 add.s, f0, f1, f2, 0x3fc00000, 0x34400000, \
- 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001
+ 0x3fc00002, 0x3fc00001, 0x3fc00002, 0x3fc00001, \
+ FSR_I, FSR_I, FSR_I, FSR_I
test_op2 add.s, f3, f4, f5, 0x3fc00000, 0x34a00000, \
- 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002
+ 0x3fc00002, 0x3fc00002, 0x3fc00003, 0x3fc00002, \
+ FSR_I, FSR_I, FSR_I, FSR_I
/* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
test_op2 add.s, f6, f7, f8, 0x7f7fffff, 0x7f7fffff, \
- 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
+ 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
+ FSR_OI, FSR_OI, FSR_OI, FSR_OI
test_end
test add_s_inf
/* 1 + +inf = +inf */
test_op2 add.s, f6, f7, f8, 0x3fc00000, 0x7f800000, \
- 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000
+ 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000, \
+ FSR__, FSR__, FSR__, FSR__
/* +inf + -inf = default NaN */
test_op2 add.s, f0, f1, f2, 0x7f800000, 0xff800000, \
- 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
+ 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
+ FSR_V, FSR_V, FSR_V, FSR_V
test_end
-test add_s_nan
- /* 1 + NaN = NaN */
+#if DFPU
+test add_s_nan_dfpu
+ /* 1 + QNaN = QNaN */
test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
- 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR__, FSR__, FSR__, FSR__
+ /* 1 + SNaN = QNaN */
test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
- 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR_V, FSR_V, FSR_V, FSR_V
- /* NaN1 + NaN2 = NaN1 */
+ /* SNaN1 + SNaN2 = QNaN2 */
+ test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* QNaN1 + SNaN2 = QNaN2 */
+ test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* SNaN1 + QNaN2 = QNaN2 */
+ test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+#else
+test add_s_nan_fpu2k
+ /* 1 + QNaN = QNaN */
+ test_op2 add.s, f9, f10, f11, 0x3fc00000, 0x7fc00001, \
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR__, FSR__, FSR__, FSR__
+ /* 1 + SNaN = SNaN */
+ test_op2 add.s, f12, f13, f14, 0x3fc00000, 0x7f800001, \
+ 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
+ FSR__, FSR__, FSR__, FSR__
+ /* SNaN1 + SNaN2 = SNaN1 */
test_op2 add.s, f15, f0, f1, 0x7f800001, 0x7fbfffff, \
- 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001
+ 0x7f800001, 0x7f800001, 0x7f800001, 0x7f800001, \
+ FSR__, FSR__, FSR__, FSR__
test_op2 add.s, f2, f3, f4, 0x7fbfffff, 0x7f800001, \
- 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
+ 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
+ FSR__, FSR__, FSR__, FSR__
+ /* QNaN1 + SNaN2 = QNaN1 */
test_op2 add.s, f5, f6, f7, 0x7fc00001, 0x7fbfffff, \
- 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001
+ 0x7fc00001, 0x7fc00001, 0x7fc00001, 0x7fc00001, \
+ FSR__, FSR__, FSR__, FSR__
+ /* SNaN1 + QNaN2 = SNaN1 */
test_op2 add.s, f8, f9, f10, 0x7fbfffff, 0x7fc00001, \
- 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff
+ 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, 0x7fbfffff, \
+ FSR__, FSR__, FSR__, FSR__
test_end
+#endif
test sub_s
test_op2 sub.s, f0, f1, f0, 0x3f800001, 0x33800000, \
- 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000
+ 0x3f800000, 0x3f800000, 0x3f800001, 0x3f800000, \
+ FSR_I, FSR_I, FSR_I, FSR_I
test_op2 sub.s, f0, f1, f1, 0x3f800002, 0x33800000, \
- 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001
+ 0x3f800002, 0x3f800001, 0x3f800002, 0x3f800001, \
+ FSR_I, FSR_I, FSR_I, FSR_I
/* norm - norm = denorm */
test_op2 sub.s, f6, f7, f8, 0x00800001, 0x00800000, \
- 0x00000001, 0x00000001, 0x00000001, 0x00000001
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, \
+ FSR__, FSR__, FSR__, FSR__
test_end
test mul_s
test_op2 mul.s, f0, f1, f2, 0x3f800001, 0x3f800001, \
- 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
-
+ 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
+ FSR_I, FSR_I, FSR_I, FSR_I
/* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
test_op2 mul.s, f6, f7, f8, 0x7f000000, 0x7f000000, \
- 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff
+ 0x7f800000, 0x7f7fffff, 0x7f800000, 0x7f7fffff, \
+ FSR_OI, FSR_OI, FSR_OI, FSR_OI
/* min norm * min norm = 0/denorm */
test_op2 mul.s, f6, f7, f8, 0x00800001, 0x00800000, \
- 0x00000000, 0x00000000, 0x00000001, 0x00000000
-
+ 0x00000000, 0x00000000, 0x00000001, 0x00000000, \
+ FSR_UI, FSR_UI, FSR_UI, FSR_UI
/* inf * 0 = default NaN */
test_op2 mul.s, f6, f7, f8, 0x7f800000, 0x00000000, \
- 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000
+ 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000, \
+ FSR_V, FSR_V, FSR_V, FSR_V
test_end
test madd_s
test_op3 madd.s, f0, f1, f2, f0, 0, 0x3f800001, 0x3f800001, \
- 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002
+ 0x3f800002, 0x3f800002, 0x3f800003, 0x3f800002, \
+ FSR_I, FSR_I, FSR_I, FSR_I
test_end
test msub_s
test_op3 msub.s, f0, f1, f2, f0, 0x3f800000, 0x3f800001, 0x3f800001, \
- 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001
+ 0xb4800000, 0xb4800000, 0xb4800000, 0xb4800001, \
+ FSR_I, FSR_I, FSR_I, FSR_I
test_end
#endif
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> --- tests/tcg/xtensa/fpu.h | 142 ++++++++++++++++++++++++ tests/tcg/xtensa/test_fp0_arith.S | 178 ++++++++++++++---------------- 2 files changed, 223 insertions(+), 97 deletions(-) create mode 100644 tests/tcg/xtensa/fpu.h